High speed, energy efficient data converters for ultra wideband communication systems

High speed, low power, and medium resolution, analog-to-digital converters (ADC) are widely used in high data-rate communication applications such as ultra wide band (UWB) and 60GHz RF systems. In such applications, ADCs with a sampling rate of giga samples per second (GS/s) and low power consumption are typically required. Traditionally, flash ADCs have been used for such applications because of their superior conversion speed in comparison with other ADC architectures. Successive approximation register (SAR) ADCs have gained popularity in recent years because of their superior energy efficiency.;This thesis introduces new ADC architectures that enable operation of energy efficient SAR ADCs at speeds comparable to those of flash ADC and which take advantage of pipelining and asynchronous processing. First, the challenges of designing conventional asynchronous SAR ADCs such as highly capacitive input, high kickback noise, and comparator offset in loop unrolled SAR ADCs are investigated and new solutions to each issue are proposed.;Next, new energy efficient, asynchronous ADCs with multi-bit quantization, minimum number of comparators, and reduced sensitivity to kickback noise are introduced to improve the speed of conventional asynchronous SAR and asynchronous, binary search ADCs. A new class of ADCs that perform the binary search algorithm in pipeline mode is also proposed. The proposed ADCs achieve operation speeds comparable to those of flash ADCs, while keeping the energy efficiency characteristics of SAR ADCs by trading latency for speed. Measurements confirm 1.25GS/s with energy efficiency of less than 100fJ/conv-step. Finally, a new class of delta sigma modulators that use finite impulse response (FIR) filters in their architecture to improve speed and energy efficiency is introduced.