Application specific interconnect design and scheduling on multiprocessor architectures

DSP applications have large number of Instruction Level Parallelism (ILP) and have stringent real time delay requirements. Multiprocessor architectures are favorable as they provide abundant computation resources. However as VLSI technology advances, the Interprocessor Communication Network (ICN) does not scale with the ever increasing computation power and it has become a bottleneck that limits the overall system performance. It is therefore important to design an ICN that is fast yet colt saving on area and energy consumption.;In this dissertation, we take an application specific approach, which differs from other research in the area and enables us to design the minimum resources required ICN without performance degradation. We propose several algorithms to design ICN with various themes. All proposed algorithms design the targeted ICNs with minimum resources required while preserving the given applications' embedded ILP.;A good scheduler is critical to exploit the abundant computation resources available in a multiprocessor architecture and to put less pressure on the ICN by minimizing the communication needs. In this dissertation, we propose several computation and communication co-scheduling algorithms for multiprocessor architectures with various ICN schemes to minimize the ICN resources required. We apply heterogeneous interprocessor data transfer policy, which also differs from other research in the area and enables us to optimally schedule the inter-processor data transfers so that the communication conflicts can be minimized.;In summary, our research focuses on developing models, methodologies and algorithms for application specific interconnect design as well as for computation and communication coscheduling techniques in order to achieve performance white minimizing the area and energy consumption of the target interconnection network. We have carried out our research on various ICN schemes including partially connected bus ICN, segmented bus ICN and 2D mesh style ICN. The target multiprocessor architecture can either be homogeneous or heterogeneous. The input applications can be either concurrently running or sequentially running on the target architecture. Promising results have been obtained which are going to be presented in the following chapters. These results significantly improve the start-of-art techniques in related areas.