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An improved bus-based multiprocessor architecture

Posted on:1998-11-12Degree:M.S.EType:Thesis
University:The University of Alabama in HuntsvilleCandidate:Ricks, Kenneth GFull Text:PDF
GTID:2468390014975972Subject:Electrical engineering
Abstract/Summary:
This thesis presents a new, cost effective multiprocessing architecture which can be constructed using off-the-shelf components. The proposed architecture extends the current generation of single-board-computer systems to include a low cost, supplemental interprocessor communication network. The resulting extended single-board-computer multiprocessor (ESBCM) architecture is shown to have improved scalability characteristics and is much more flexible than current multiprocessor designs. It also directly supports many real-time and fault-tolerant constructs not previously supported. Extensive empirical analysis using discrete event simulations and Monte Carlo techniques indicate that the ESBCM architecture will generally outperform standard bus-based multiprocessors.
Keywords/Search Tags:Architecture, Multiprocessor
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