| High density data storage is critical for today's explosive growth in memory intensive applications. To meet such demands, various emerging devices have been extensively explored including three-dimensional (3D) devices based on CMOS technology, which is by far the most promising candidate for realizing the ultra-high-density storage in the near future. However, to date, there is no 3D chip architecture integrating the 3D memory devices and peripheral devices in a wafer level, which can significantly increase the storage capability beyond physical scaling limits.;In this dissertation, I present a novel 3D memory chip architecture of Stacked-Memory-devices-On- Logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. The SMOL opens a new way to achieve higher memory density, lower power consumption, and faster system speed, which is beyond today's memory technology. In order to realize the SMOL, unique 3D Flash memory devices and vertical integration structure have been successfully developed. The 3D memory devices have been newly developed with various types of structures (VRAT, VSAT, CF-VSAT) and optimized for performance and feasibility. An innovational interconnection structure of PIPE ( Planarized-Integration-on-the-same- PlanE) provides a more convenient and cost-efficient way than a conventional stair-like structure. Furthermore, extensive simulations using TSUPREM4(TM), MEDICI(TM), and SANTAURUS(TM) support the scalability, wide process window of the 3D memory devices. The SMOL technology has great potential to achieve tera-bit level memory density and impacts other emerging devices to develop new 3D chip architectures. |
