| With the increasing demand for massive data storage,high-density flash memory with the advantages of large capacity,low cost and lightweight is widely deployed in consumer and enterprise server scenarios.However,as technology scaling,such high-density flash memory faces serious quality-of-service(QoS)problems caused by reliability and lifetime degradation.In order to better apply high-density flash memory to meet user access requirements,this paper conducts in-depth research on multiple issues that arise during the deployment of high-density flash memory,from application access behavior characteristics,flash memory controller algorithms to flash reliability,we make detailed analysis to solve the serious tail latency problem caused by the flash error correction process,improve data reliability when gray-code is used for data encoding,study the problem of read performance degradation caused by page latency differences,and solve serious read and write conflicts caused by latency differences between read and write requests,etc.,and propose detailed solutions and scheme designs.The main research works of this paper are as follows:(1)Research on high-density flash memory refresh technology based on LDPC error correction perception: Aiming at the tail latency problem of high-density flash memory based on Low-Density Parity-Check Code(LDPC)error correction codes(ECCs),a set of smart refresh methods are proposed,including a threshold-based refresh method and a periodic refresh method.Aiming at the degradation of read performance and severe latency spikes caused by data with long access latency,the proposed refresh method detects data access conditions to determine whether refresh is required to ensure its performance.Detection is performed in a variety of ways,including detection when processing user data access and periodic detection in the background.And rewrite the data that meets the refresh requirements to ensure the user’s access performance.Furthermore,in order to reduce the overall refresh overhead,a dual-ECC method is proposed to encode and decode data using error correction codes with different strengths for data with different bit error rates,thereby reducing the overall refresh overhead.Experimental results show that the proposed refresh scheme can effectively reduce tail latency.(2)Research on high-density flash memory data encoding technology based on multiple-gray-code: In-depth analysis of the reliability characteristics of high-density flash memory storage media,and optimization of read and write performance from the perspective of gray-codes and two-step programming algorithms.Considering that a single gray-code design cannot meet complex and changeable application requirements,nor can it achieve stable access performance against the reduced reliability problem after flash wearing.This research work provides an in-depth analysis of the characteristics of different gray-codes and two-step programming algorithms.Then,the appropriate gray-code and two-step programming algorithm are selected in combination with application requirements and device-side reliability characteristics.A multiple-gray-code(MGC)arbitration method is proposed to improve the performance of each reliability stage of flash memory.Experimental results show that MGC can improve read performance by 26% on average and up to 51% in the Middle stage compared to the state-of-the-art.In the Old stage,the average read performance is increased by7.4%.(3)Research on high-density flash memory data layout technology based on page latency variation perception: By exploring the page access latency of high-density flash memory,it is found that there are differences in access performance between different types of flash pages.By analyzing the data access characteristics,a data placement method is proposed to maximize read performance.The basic idea is to detect the read hotness of user data,place hot read data on low-latency pages,and cold read data on high-latency pages,thereby optimizing read performance.Further,the access characteristics of metadata are studied,and a reliability stage aware metadata placement method is designed to accelerate metadata access.Finally,to avoid latency spikes,a caching method is designed for reducing the number of accesses to high-latency pages to achieve tail latency optimization.Experimental results show that the proposed method can improve read performance by an average of 46% compared to the state-of-the-art.For the tail latency problem,the design method can reduce the latency by 63%at the 95 th percentile,65% at the 99 th percentile,74% at the 99.9th percentile,and 77% at the 99.99 th percentile.(4)Research on high-density flash memory partition technology based on read-write interference awareness: Considering the serious readwrite interference problem in high-density flash memory,a partitioned SSD architecture with read and write characteristics awareness is proposed.The flash memory array is physically divided into a read area and a write area according to the granularity of the parallel unit,and then design a data placement method according to the read and write characteristics of the data,place frequently read data in the read area,and place frequently updated data in the write area.Therefore,most read and write requests can be separated.This is because read and write requests can be processed by different parallel units to avoid read and write interference.Furthermore,in order to ensure consistent wearing of parallel units between partitions,a novel wear leveling method based on the partitioned SSD architecture is proposed to ensure the lifetime of flash memory.Finally,the proposed partitioned SSD architecture can effectively reduce the read-write interference in high-density flash memory.Experimental results show that the proposed method can improve read performance by an average of 45% and up to 86% compared to the state-of-the-art.In summary,a series of optimization strategies proposed in this paper can effectively improve the QoS of high-density flash memory.The QoS referred to in this paper mainly includes the average access performance of flash memory and the tail latency(i.e.,the latency at the 99th-99.99 th percentile).Therefore,our proposals provide QoS optimization of flash memory to achieve stable flash access performance and superior user experience when high-density flash memory is deployed in real scenarios. |
