Optimal defect-tolerant SRAM designs in terms of yield-per-area under constraints on soft-error resilience and performance

Since the advent of computer-aided design (CAD) of digital systems, technological constraints and advancements as well as market forces have been major drivers of the direction of design methodologies. We have seen the emphasis shift from area minimization in the LSI era, to delay minimization in the early part of VLSI era, and to power minimization in the recent decade. Given current technology trends, the IC industry will soon need to address the next paradigm shift in CAD of digital systems, since digital system design will soon confront computing technologies and fabrication processes with extremely high levels of variations in the values of key parameters, such as defect densities and soft error rates. While defect-tolerance (DT) and faulttolerance (FT) techniques have matured over the past 50 years, they have been applied to a limited class of digital subsystems and in an era of relatively low defect densities and low soft error rates. Furthermore, FT techniques have been largely confined to avionics and other critical systems where cost is not a main objective. In contrast, we must soon apply these approaches to the entire range of digital systems, including those with strict constraints on cost, performance, and power. A direct extrapolation of how DT/FT techniques are currently applied will erode much of the benefits of new processes/technologies. Our early results clearly show that careful application of DT/FT techniques will provide significant gains in the near future and will become increasingly important thereafter. Our results also show that a large space of possible ways of applying these techniques must be searched carefully to obtain efficient designs. This makes it imperative to develop new systematic approaches to efficiently apply current and new DT and FT techniques to all digital systems.;The objective of this dissertation is to develop new comprehensive methodologies for designing defect-tolerant memory devices optimized in terms of yield-per-area under high defect rates and high soft error rates where soft-error resilience and performance are given as constraints. Memories are significant proportions of most digital systems and memory-intensive chips continue to lead the migration to new nanometer fabrication processes. Thus, improving the reliability and robustness of such memory devices will be very crucial issues. As for hard defects, competitive pressures require SRAM and i-processor vendors to adopt the latest process before it has matured and hence when it suffers from high defect rates. Also, SRAMs are becoming more susceptible to soft errors with each process generation [95][101] [103]. SRAMs may thus require increasing numbers of spares and stronger error correcting codes. Under those circumstances, we explore optimal SRAM architecture in terms of yield-per-area for given constraints on performance and soft error rates, by considering various design alternatives, including granularities (characterized by sizes of memory sub-arrays), spare switching schemes, error correcting codes, and physical layouts.;Our models and experiments demonstrate that (1) the optimal granularity tends to be finer with the increase of defect densities, while it tends to be almost independent of memory size for a given defect density, (2) the use of spares is more useful for optimization than physical layout changes, (3) interconnects between memory sub-arrays tend to have impact on memory yield that is much greater that its proportion of memory area, especially for high defect densities and large number of sub-arrays, and (4) the integrated use of ECC and spares for hard defects can reduce the required number of spares, thereby decreasing area and performance penalties.