Research And Circuit Imp. Of SRAM Soft-Error Detection And Correction

BISR (Built in Self Repair) circuit is designed to achieve the natural correction of internal error automatically. In order to supervise 176bit wide parallel data, one novel method, which is based on extended-hamming codes, has been proposed.This paper includes two objectives:Firstly, duo to the XOR exchangeable calculation feature, a Signature-map has been constructed, which can be used to rearrange the XOR-Tree. In that way, the numbers of XORs between pre-optimized and post-optimized can be reduced.Secondly, based on the TSMC 90nm process and optimized XOR-Tree, the circuit has been designed in physical level.There are mainly four keys in this paper:(1) To study the history and present modified technology of ECC (Error Correct Code), and then analyze the good effects and weak points of these technologies. These works can demonstrate a preliminary scene of ECC.(2) Based on the main encode and decode techniques, some known algorithms have been compared during evaluating the project.(3) Refer to some previous works, a Signature-map figure has been designed to optimize the XOR-Tree structure. In the principle of guarantee the circuit function, redundant logic cells have been reduced to save the circuit.(4) To design ECC circuit in physical level, the work we have taken contains analysis and optimization of timing, area and power. After that, the results between pre-optimize and post-optimize have been compared. Furthermore, some suggestions about circuit improvement have been proposed. The simulation results show that, 28% of delay, 35% of area and 36% of power have been reduced. At last, ECC delay is 1.5ns, area, 6200μm2 and average power dissipation, 0.54mW. These data prove the effectiveness of our methods.This research indicates that, for the duplicate part of SRAM, circuit structure analysis should be taken firstly. For example, standing on the formula optimization of extend-hamming code, Signature-map proposed in this paper can be used to analyze structure visually and effectively. This also gives some advice for future IC topology and design advances.