Smic 0.35um Process Sigma-delta Adc Design And Verification

Sigma-Delta analog to digital converter (ΣΔADC) in the use of oversampling and noise shaping technology are two key technologies, which makes anti-aliasing requirements are very low, and signal band quantization noise power is suppressed. Filtered high-frequency noise outside the signal band with the decimation filter, signal to noise ratio and dynamic range would be enhanced, and reduced precision requirements on the analog circuit.In-depth study of theΣΔADC based on the principle, and design aΣΔADC based on SMIC 0.35um. The use of feasible effective verification and simulation tools to test results.First, according to indicators in the Matlab\Simulink platform design behavioral model of the modulator to model non-ideal factors, design reasonable magnification, slew rate, bandwidth and the decimation filter and down-sampling rate of progression through the simulation After determining the performance requirements of the circuit-level design.Second, the design of the modulator circuit and decimation filter Verilog-HDL code, respectively, simulate with the Hspice and Co-Simulation, and field programmable gate array (FPGA) integrated out a decimation filter circuit. The establishment of the FineSim Pro hybrid simulation platform module, written interface circuit to integrated modulator and decimation filter, obtained the last SNR and effective reach the design specifications.Finally, this paper is based on SMIC 0.35um process, using Cadence's Virtuoso Layout software to design the modulator part of the full-custom layout, and using Synopsys's Design Compiler (DC) to integrate a decimation filter circuit, and using the Astro to complete decimation filter layout. All layout had been past through DRC and LVS inspection.This in-depth study based on the principle ofΣΔADC, using the correct verification methods and simulation tools designed theΣΔADC. Obtained from the results proved the effectiveness is demonstrated, using the tools of rationality, greatly reducing the simulation time and shorten the design cycle.