Delta-Sigma FDC Based Fractional-N PLLs with Multi-Rate Quantizing Dynamic Element Matching

Fractional-N phase-locked loop (PLL) frequency synthesizers are ubiquitous in modern communication systems, where they are used to synthesize a signal of high spectral purity from a reference signal of much lower frequency. In order to meet the requirements of wireless communication standard, strict limitation are placed on the spectral content of the synthesized signal.;In recent years, PLL based on time-to-digital converters (TDC-PLLs) have been proposed that aim at moving the complexity of the design from the analog section to the digital section of the synthesizer: the advantages are a reduction in area, cost and power consumption over competing architectures based on delta-sigma modulation and charge pumps (DS-PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase noise and spurious tone performance below that of the best comparable DS-PLLs. An alternative approach is to use a delta-sigma frequency-to-digital converter (DS FDC) in place of a TDC to retain the benefits of TDC-PLLs and DS-PLLs.;Chapter 1 describes a practical DS FDC based PLL in which the quantization noise is equivalent to that of a DS-PLL. It presents a linearized model of the PLL, design criteria to avoid spurious tones in the DS FDC quantization noise, and a design methodology for choosing the loop parameters in terms of standard PLL target specifications.;Chapter 2 presents a multi-rate quantizing dynamic element matching (DEM) encoder for digital to analog converters (DACs) that allows a significant reduction in the encoder power consumption with respect to a conventional encoder for oversampling DEM DACs, at the expense of a minimal signal-to-noise ratio reduction.;In Chapter 3, the implementation details of a DS FDC based fractional- N phase-locked loop prototype are shown. The PLL was built to showcase the capability of the architecture analyzed in Chapter 1 to comply with the most stringent wireless communication standards. The prototype extends the architecture described in Chapter 1 by including an FDC quantization noise cancelling algorithm, and an hardware efficient implementation of a multi-rate quantizing DEM encoder for digital to frequency conversion.