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Using Integrated Circuits as Virtual Test Structures To Extract Defect Density and Size Distributions

Posted on:2011-03-26Degree:Ph.DType:Dissertation
University:Carnegie Mellon UniversityCandidate:Nelson, Jeffrey EFull Text:PDF
GTID:1448390002469609Subject:Engineering
Abstract/Summary:
As minimum feature size continues to shrink and an ever-increasing number of transistors are integrated onto a single die, yield-learning activities become more important than ever to manufacture working chips. One key yield-learning task to understand the impact of random defects is to extract and monitor defect density and size distributions (DDSDs). Traditional methods using test structures and inline optical inspection are expensive and limited. A technique called DICED is investigated that uses only integrated circuit (IC) product test results to derive DDSDs that characterize bridge defects in back-end metal layers.;One necessary prerequisite for DICED is a set of chips that fail due to bridge defects. An automatic bridge classification (ABC) technique is described that identifies bridge defects that can be used by DICED.;In simulation experiments using benchmark circuits and artificially injected defects, ABC identifies a set of chips that consists of over 95% bridges. Using this set of chips, DICED extracts DDSDs with 0% error for several metal layers when a highly accurate logic diagnosis tool is used. ABC and DICED are also applied to a commercial graphics processor unit (GPU). The sheer scale and diversity of the design exposes limitations of both techniques. Several modifications are proposed to make ABC and DICED practical in commercial environments. One variant of DICED addresses scale and diversity by extracting only average defect density. When validated using simulation of artificial defects in benchmark circuits, three metal layers are extracted with 0% error.;When using DICED, the product IC acts as a virtual test structure (VTS), providing a vehicle for deriving important defect metrology. The product covers a large majority of the wafer area, thus when used as a VTS, it has excellent observability of defects---even during phases of the process lifecycle when test structures are minimally used.
Keywords/Search Tags:Test structures, Defect, Size, Integrated, Using, DICED, Circuits, Used
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