Test Generation For Integrated Circuits At Register Transfer Level

Design verification or validation and test are significant for good functionality and reliability of Integrated Circuits (ICs). Sequential circuit Automatic Test Pattern Generation (ATPG) is then very important, but difficult as widely recognized. The dissertation targets the problem for commonly used Register Transfer Level (RTL) behavioral descriptions and proposes a very effective method, to generate test sequence for both design validation and functional test. The original ideas include the following.1. Precise and concise abstract representations of RTL behavioral descriptions are proposed. The representations include Process Controlling Trees (PCT), Data Direction Graphs (DDG), and Defined Behavior Graphs (DBG), which express control structure, data relation, and circuit behavior of processes respectively. The representations construct the basis of the implementation of the proposed method.2. A behavior tendency driven engine to reveal circuit behavior is proposed. For a present state, a behavior tendency is defined to be a state transition, which has the most possibility to reveal circuit behavior. The engine is efficiently used to drive a target circuit to behavior tendencies of present states from the initiate state, which will generate a state transition sequence to reveal circuit behavior and its corresponding input sequence. 3. A backtrack-free RTL ATPG algorithm based on the engine and a kind of RTL transfer fault model is presented. Transfer faults are defined. It is expected to test both design functionality and chip faults by testing transfer faults. The ATPG is backtrack-free ATPG, and implemented based on the behavior tendency driven engine in order to remarkably improve efficiency. Experimental results for ITC99 benchmarks demonstrate that the proposed ATPG method can speed up the Genetic-Algorithm-based RTL ATPG by more than 3 orders of magnitude.Furthermore, the length of the generated test sequence is reduced by 4% and the corresponding gate-level stuck-at fault coverage is increased by 0.2% on an average. This illustrates that the proposed method in the dissertation can generate test sequences more efficiently with comparable or even better quality, and therefore, it is effective and practical.