Research On Key Technologies Of Dynamic Reconfigurable Cryptographic Chip

Cryptographic chip is an important foundation in information security systems.The architecture of dynamically reconfigurable computing technology has the potential to be widely used in the field of cryptography.However,current dynamic reconfigurable cryptographic chips still have problems that are difficult to balance flexibility,energy efficiency and security.It is mainly reflected in three aspects: first,how to adapt to the needs of the diversity of cryptographic algorithms;second,how to improve the execution efficiency the irregular cryptographic dataflow graphs;and the third is how to improve the hardware security of the chip using the features of reconfigurable computing.This paper focuses on solving the problems of dynamic reconfigurable cryptographic chips that combine high flexibility,high energy efficiency,and high security.First,the structural characteristics and reconfigurability of common cryptographic algorithms and typical security protocols are analyzed.And base on that,an innovative exploration of key technologies is carried out on the hardware architecture of dynamic reconfigurable cryptographic chips.A design method for operators and interconnections in the field of cryptography is proposed.Through the quantization and frequency analysis of basic operators,the design of homogeneous and heterogeneous processing units is completed.A configurable replacement-broadcast interconnection is designed.The network enhances chip flexibility and energy efficiency by converging cryptographic operations with operator interconnects.The experimental results show that the datapath can support the algorithms required by the security protocol.Compared with DBN/SRBMC and other similar designs,the interconnection network increases the operating frequency by 33% and reduces the number of routing units by 65%.Second,a full-connected array structure based on block partitioning is proposed.This array is divided into reconfigurable blocks,and data is exchanged between blocks at high speed through hierarchical multi-level cache,which effectively enhances the locality of feedback/iterative type cryptographic calculation and improves the operating efficiency.The experimental results show that 55% acceleration can be achieved compared to the datapath without this technology.The third is to propose configuration merging and coding compression technology.By continuously executing the loop body in a single configuration and computing branches in parallel,the number of reconfigurations is effectively reduced.The configuration code is reduced by the extraction of similarity and compression of the configuration code.The experimental results show that more than 15 times of configuration acceleration and more than 80% of configuration code compression can be achieved compared to that does not use this optimization technique.The fourth,for the safety of implementation and storage of configuration code,a random configuration technique based on equivalent reconfigurable blocks is proposed,which introduces time and spatial randomness for algorithm execution.A configuration code scrambling technology based on SPUF is proposed to increase the physical attacks resistance level of cryptographic chip;and,a SPUF circuit based on differential charging capacitor is designed,the test result shows that the circuit has better temperature stability,power consumption,and performance than the works from JSSC'16 and DATE'16.The above technologies are implemented on a dynamic reconfigurable cryptographic chip and a SPUF circuit verification chip with TSMC 55 nm process.The TSR chip can perform cryptographic suites and algorithms acceleration in common security protocols.The performance is more than 6 times that of the best one of the current workCryptoraptor,and the area efficiency is improved by about 60%.The SPUF circuit test results show that compared with the results of JSCC'16,the power consumption is reduced by 61.9% and the performance is improved by 2.8 times..