Research On Novel Power Field-Effect Transistor

Electrical energy is one of the most widely used forms of energy at present.From the generation to the use,it is inevitable to perform related processing on the electric energy through a certain technology to change the magnitude of its voltage,the strength of its current,the numerical value of its frequency,etc.Power electronics technology is the technology that efficiently transforms,controls,and regulates electrical energy,whose core is power semiconductor devices.Power semiconductor devices have two structural styles,"lateral"and"vertical".Lateral power semiconductor devices,represented by lateral power field-effect transistors?LDMOS?,have the advantages of easy driving and integration,and fabricating themselves with their own control circuits on the same chip can effectively reduce the cost and improve the reliability.However,at the same voltage class,the lateral power semiconductor device generally has a larger cell size,a lower current capability,and a higher conduction voltage drop than a vertical power semiconductor device.In response to the above problems,the author has carried out a series of research work on LDMOS.The innovative contents of this dissertation are as follows:1.A superjunction LDMOS?SJ-LDMOS?with a carrier accumulation layer is proposed.In the proposed SJ-LDMOS,there is a thin oxide between the P-pillar and the N-pillar for isolation.This oxide not only reduces the difficulty of controlling the accuracy of doping of the pillars,but also helps to form accumulation layers in the drift region when the device is in the on-state,which accounts for a decrease of 35%in the specific on-resistance(R_on,sp)and an improved current capability for the proposed SJ-LDMOS,compared with the conventional SJ-LDMOS of the same voltage class.In addition,since the composition of the reverse transfer capacitor?the depletion region capacitance in series with the gate oxide capacitance?is reduced because of the capacitance composed of the P-pillar,the oxide,and the N-pillar,the proposed SJ-LDMOS with a carrier accumulation layer has a lower gate drive loss.2.In a totem-pole half-bridge circuit,to effectively simplify the low-voltage control circuit,the high-side device and the low-side device are supposed to be p-LDMOS and n-LDMOS,respectively.However,at the same voltage class,p-LDMOS has lower current capability and higher R_on,sp than n-LDMOS,which indicates that if p-LDMOS is desired to achieve the same current capability as n-LDMOS,it will take up more chip area.In order to solve this problem,an LDMOS with both types of carriers participating in conduction is proposed.By utilizing high-mobility electrons,the current capability of the device is greatly enhanced.Although the proposed LDMOS is a dual-gate device with two parallel structures of n-LDMOS and p-LDMOS,one gate of them for controlling the path for electrons flowing?the n-LDMOS structure?is automatically controlled by the signals acquired in the device and an integrated circuit.The n-LDMOS thus turns on and off spontaneously and in synchronization with the p-LDMOS.Therefore,from the perspective of the external electrodes,the proposed LDMOS is still a p-LDMOS of three terminals.3.An LDMOS with high-k dielectrics covering the surface is proposed.The mechanism of high-k dielectric for LDMOS is to introduce additional electric flux into the surface of the latral voltage-sustaining region,due to the potential difference between themselves,to optimize the electric field distribution.Therefore,under the condition of the same size,the breakdown voltage?V_B?of the proposed LDMOS is improved by 24%compared with the conventional LDMOS.In addition,since the electric field lines have a nature of flowing into a region with a high permittivity,when the device is in a state of blocking and voltage-sustaining,in the drift region with a higher doping,electric field lines generated by the ionized impurities flow through high-k dielectrics and barely affect the surface electric field distribution?namely the V_B?.However,the R_on,sp of the device is consequently reduced by 13%.4.LDMOS with a deep trench has a smaller cell size by“folding”the drift region inside,which is typically located on the surface.It is an effective way to further optimize the compromised relationship between the R_on,sp and the V_B.Based on this basic structure,an SJ-LDMOS with deep trenches is proposed,which has two paths for conducting current.The R_on,sp of the conventional deeply-trenched LDMOS is constrained by the dose of the drift region that is related to the V_B.In contrast,the R_on,spn,sp of the proposed SJ-LDMOS can be further reduced without sacrificing the V_B.