Optimal Design And Experimental Research Of A Novel Lateral High Voltage Devices With Homogenization Field Voltage Sustaining Layer

Power semiconductor devices are the core of the power processing field and are widely used in high-voltage and high-power circuits.With the advocacy of low-carbon life,electric energy,as a green energy,has greatly promoted the sustainable development of society,and various electrical equipment can operate only by virtue of the conversion of electric energy by power semiconductor devices.However,for power devices,the breakdown voltage V_B and the on-resistance R_on,sp are a pair of contradictions that are difficult to reconcile,so many device structures have been proposed to optimize the two.From the resistive voltage sustaining layer VDMOS(Vertical Double-Diffusion MOSFET),to the conductance enhanced resistance voltage sustaining layer IGBT(Insulated Gate Bipolar Transistor),to the junction voltage sustaining layer SJ(Super Junction),all follow the optimized voltage sustaining layer.The concept of layers is used to realize innovative design of devices.Adhering to the above ideas,the author's team proposed the concept of HOF(Homogenization Field)voltage sustaining layer and applied it to LDMOS(Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor)devices,through the MIS array periodically arranged in the drift region,achieving global depletion in bulk and further increasing the doping concentration.In this tesis,a new device structure is proposed based on the research of HOF voltage sustaining layer,and the optimized design is carried out.The main contents and achievements of this subject are as follows:(1)Based on the existing HOF LDMOS experiments,the mechanism and characteristics of the HOF voltage sustaining layer were further studied.When the doping concentration is higher than a certain value,the breakdown voltage is greatly reduced.On this basis,according to the charge self-balancing principle of MIS(Metal Insulator Semiconductor)structure,a D-HOF(Double HOF)device is proposed.It is characterized by introducing a P-top layer on the surface of the S-HOF drift region.When the device is off,the P-top is almost completely depleted by the MIS array and N-drift,and the surface field of the D-HOF voltage sustaining layer will be depleted by the surface.The P-top layer is clamped,so when the doping concentration of N-drift changes in a wider range,the surface field of the device does not change,which prevents the surface breakdown of the device to a certain extent.(2)The problem of early breakdown of D-HOF devices with long drift region is analyzed.It is found that there is a strong curvature effect at the bottom of the last periodic MIS trench close to the drain electrode,resulting in a local electric field peak at the bottom of the trench wall,which is the root cause of the early breakdown of the device.By studying the mechanism of the curvature effect,starting from the three paths to solve the curvature effect,a process-compatible optimization scheme is proposed,and the TS-HOF device structure is designed,which is characterized by the drain end of the trench to cut off the depletion of the last MIS groove,to suppress severe 3D volume curvature effects.Experiments show that the V_B of the TS-HOF LDMOS is more than 15%higher than that of the D-HOF device of the comparative structure,while maintaining almost equal on-resistance R_on,sp.The measured V_B of the TS-HOF LDMOS is 675 V,and the R_on,sp is49.1 m?·cm~2,which is a 43.2%reduction compared to the theoretical value of the Triple RESURF technology.(3)SOI-HOF structure is proposed.By introducing a buried oxygen layer,the curvature effect of bulk is completely eliminated.Inserting the MIS structure electrode into the buried oxide layer can realize ENDIF,withstand high voltage through the insulator,optimize the longitudinal electric field,and improve the breakdown voltage of the device.Under the condition that the length of the drift region is 46?m,the simulation realizes the characteristics of the withstand voltage of 910 V and the electric field of the insulator layer of 424 V/?m.