Optimization Design And Application Research Of The Charge Balance Voltage-sustaining Layer Structure

Global climate warming and energy crisis make strict requirements on the efficient use of electricity. Power electronics is the most advanced electrical energy conversion technology. And the power semiconductor device is the core part in power electronics. People are looking for “the perfect power semiconductor device” which demands low driving, conduction, off-state and switching power dissipation. Each mainstream device on the market can only meet a part of these requirements. The charge balance voltage-sustaining structure studied in this thesis is the research hotspot in the area of silicon-based power semiconductor devices. It can enhance significantly the performance of vertical and lateral devices, as well as the junction termination, making devices be closer to be “perfect”. The charge balance principle find its widely application in power semiconductor devices, including the superjunction structure, various reduced surface field structures, the optimum variation lateral doping structure, and et al. After reading and learning many papers, the author find that the charge balance voltage-sustaining layer can be optimized further and some problem exists in its application. For example, the substrate assisted depletion effect results in a low breakdown voltage in a Lateral Double-diffused Metal-Oxide-Semiconductor field effect transistor(LDMOS) on a silicon substrate. And how to realize the previous researcher’s innovative structure with the domestic existing process, et al. Aiming at above problems, the author carries out a series of researching work under the instruction of Professor Chen Xingbi. The main innovation work includes:1. An improved superjunction structure which has three segment variation vertical doping profile to reduce the specific on-resistance further is studied. The introduction of the variation vertical doping profile reduces the peak electric field of the original structure, making the electric field profile be more uniform and raising the average concentration in the superjunction column. This structure is decomposed into a conventional superjunciton structure part and a PIN diode structure part,based on the charge superposition principle, to obtain electric field profile models by solving Poisson’s equation. Structures rating from 400 V to 1600 V with column width b = 5 μm and b = 12 μm are optimized with the help of the numerical analysis software MATLAB. The results show that their trade-off relations between the specific on-resistance and the breakdown voltage are better than that of the conventional structure. The specific on-resistance is reduced by 10% for the same voltage rating devices. Further, a process simulation verifies that a 600 V rating metal-oxide-semiconductor field effect transistor with a column width b = 5 μm performs a 7.7% reduction in the specific on-resistance, without extra process steps.2. This thesis promotes a novel LDMOS structure, which is based on a deep drain diffusion combined with field plates, to solve the substrate assisted depletion effect which limits the breakdown voltage of the bulk silicon charge compensation LDMOS. The substrate assisted depletion effect is explained by the curvature effect of the drain diffusion. The reason of increasing the breakdown voltage by weakening the curvature effect using the deep drain diffusion combined with field plates is analyzed. The junction depth of the drain diffusion and structure parameters of the field plates are design optimally with the help of 3-D simulation software DAVINCI. The results show that the figure of merit of the novel structure is increased by about 20%, compared with the classical solution employing reduce surface field technique. And the process window of the breakdown voltage towards charge imbalance is increased to ± 4%. The turn on time and turn off time are 10 ns and 30 ns respectively for a 700 V rating device under a resistance load. A feasible manufacture process flow is provided. The process simulation shows that the high temperature procedure will influence the doping profile but will not influence the optimal results.3. Based on the patents about the optimum variation lateral doping structure of Professor Chen Xingbi, an 800 V smart power integrated circuits process platform is developed. This process platform can integrate both lateral and vertical high voltage power devices on a single chip, by adding only several process steps in a standard Complementary Metal-Oxide-Semiconductor(CMOS) process flow. It uses 12 photolithography steps with 11 masks. The structure and flow of the process platform are analyzed in detail. And the design of the process parameters, especially the dosage of each layer in the optimum variation lateral doping structure, are discussed. Integrated devices, such as the 800 V high voltage power devices, the 40 V medium voltage CMOS devices, the electronic static discharge protection device, the field gate oxide device, and et al, are tested and analyzed. At last, the practicability of the process platform is verified by an off-line switching mode power supply chip.4. Based on the patents about the optimum variation lateral doping structure and high speed Insulated Gate Bipolar Transistor(IGBT) of Professor Chen Xingbi, a 1700 V high-low voltage integration process platform is developed. Several process steps are added in a mature planar gate non-punch through IGBT process flow to integrate low voltage control circuits. A “Front→back→front→back” procedure is used in the process flow to activate back impurities and the lift-off process is used to fabricate two metal electrodes on the back side. There are 16 masks in the process platform, 13 masks for the front side and the other three for the back side. The breakdown voltage, threshold voltage and forward conduction current density of the IGBT are 1900 V, 8 V and 45 A/cm2, respectively. The breakdown voltage of the low voltage NMOS and PMOS are 15 V and 21 V, respectively. Their conduction current densities are low.