Research Of High Voltage Novel Structure Of Silicon Carbide LDMOS Devices

With the acceleration of the intellectualization process of human society and the increasing popularity of large data and artificial intelligence technology,the demand for microelectronic devices has increased nonlinearly.The third generation semiconductor materials,represented by SiC and GaN,have effectively improved the performance index of power semiconductor devices with their excellent physical and chemical properties,thus solving the problem caused by material limitations of silicon-based power semiconductor.They have met the needs of high-voltage,high-frequency,high-power,high-temperature and radiation-hardness power semiconductor in various industries and fields of national economy,such as aerospace,intelligent equipment,intelligent transportation,internet of things,consumer electronics and so on.Compared with vertical discrete devices,LDMOS is widely used in various intelligent devices because of their advantages of easy integration and smaller inherent gate charge.However,the research on SiC LDMOS devices still suffers from the contradictory relationship between breakdown voltage and on-resistance.At the same time,the SiC/SiO2 interface degradation,which is limited by SiC lattice properties,is still a problem for SiC LDMOS devices.The contradictory relationship between breakdown voltage and on-resistance of SiC LDMOS devices,low mobilities of channel reverse layer caused by SiC/SiO2 interface degradation and inadequate reliability research,have seriously affected the performance and application of devices.Therefore,study of the electric field modulation principle and process feasibility design of SiC LDMOS devices in deep,optimization of the compromise relationship between breakdown voltage and on-resistance,improvement of channel reverse layer mobilities and device reliability contribute to promote the commercial process of SiC LDMOS devices.In this paper,the basic goal is to optimize the compromise relationship between breakdown voltages and on-resistances of SiC LDMOS devices,and to ensure high voltage level of devices under the help of properties of high breakdown voltages in SiC.We discuss the electric field modulation principle of SiC LDMOS devices under the above condition.The improvement of breakdown voltages,power loss and response speed of SiC LDMOS devices is realized by improving the quality factor of devices by optimizing sensitive parameters of the breakdown voltage and increasing the drift region doping concentration used the technology of electric field modulation.Therefore,the main work of this paper is as follows:(1)We systematically comb and generalize semiconductor physics equations and quantum statistical models used in the design and simulation research of high voltage SiC LDMOS devices.And model parameters have been corrected according to the theory and results of references.The guiding ideology of SiC LDMOS device design is also generalized and condensed in this paper.Exerting excellent microelectronics features of SiC material,correcting the technical orientation of Si LDMOS device design,exerting the interaction affect between SiC materials and device structure on the performance of devices,and making a "1+1>2" effect on device performances are the research core in this paper.(2)In order to solve the contradiction relationship between breakdown voltage and on-resistance of LDMOS,based on RESURF principle,ENDIF,PSOI and VLT technology,a novel lateral power device with double L-shaped buried oxide layers-DL-SiC LDMOS is proposed.In this device,fixed charge is accumulated by corners of L-shaped buried oxide layers,and the electric field in the drift region is enhanced by enhancing the electric field of buried oxide layers.SiC windows between the double L buried oxide layers below the drift region and the active region relieve the restriction of the buried oxide layer on the vertical electric field expansion and the heat dissipation in the active region.The DL-SiC LDMOS can also increase the breakdown voltage,optimize the figure-of-merit of the device and improve the heat dissipation performance of the device.(3)In order to solve the process reliability problem of the DL-SiC LDMOS due to quality defects of SiC/SiO2 interface,based on the design experience of the DL-SiC LDMOS.a novel bulk SiC lateral power device with the step compound drift region-SC-LDMOS is proposed.The distribution of the lateral surface electric field in the drift region of the device is optimized by using the VLT technique.Multi RESURF technology is used to enhance the vertical electric field and then the breakdown voltage of the SC-LDMOS devices is increased The step compound drift region can also reduce the on-resistance of the SC-LDMOS by increasing the doping concentration of the drift region surface.The proposed device can overall compromise optimization of the figure-of-merit,switching speed and heat dissipation performance.(4)The research on the breakdown voltage performance of the SC-LDMOS is extended to the radiation environment.The influence of single event effect on the breakdown voltage of the device is investigated.The SEB effect of the SC-LDMOS is suppressed by the method of P+source region expansion.In the process of studying the damage of single event effect of the SC-LDMOS,according to the objective fact that the critical electric field of SiC is similar to that of SiO2,and the knowlege that the material and structure of the device have an interactive effect on the breakdown voltage of the device,we think that the difference between the SEB threshold and the SEGR threshold is not too large in SiC LDMOS,and there is no fixed model of the damage of single event effect in 4H-SiC LDMOS,such as "the SEB damage is easy triggered in Si LDMOS".The triggering of single event effect in SiC LDMOS is mainly affected by the characteristics of the device structure.Both SEB and SEGR can be firstly triggered.In this paper,the simulation results of single event effects on the SC-LDMOS support this viewpoint.