Research On Key Technologies Of The Novel Hybrid CMOS Successive Approximation Register Analog-to-digital Converter

Analog-to-digital converter(ADC)is the interface between analog system and digital system,which is the important part of electronic system.With the rapid development of integrated circuit technology,ADCs are widely used in more and more field.Especially to the wireless communication and intelligent sensor,the performance requirements of ADCs are continuously increasing.New hybrid successive approximation register analog-to-digital converter(SAR ADC)has become the new research hotspot due to its low power consumption,simple structure and good process adaptability.Based on the diversified demand of application market and the trend of energy saving and environmental protection,this dissertation focuses on the system architecture and design method of the new hybrid SAR ADC with low power consumption,medium-high speed,and medium-high precision.As SAR ADC is the design basis of all new hybrid SAR ADCs,its key circuits are studied here,including several practical DAC switching methods,sampling switch,comparator,asynchronous clock generator circuit and SAR logic circuit.In order to meet the requirement of high precision,a gate voltage bootstrapped switch with high sampling accuracy is proposed.By using substrate bias elimination technique,the charge injection differential error is reduced and the linearity of on-resistance is improved.Pipelined SAR ADC is one kind of the new hybrid structure SAR ADCs which combines pipelined ADC and SAR ADC.Due to the perfect trade-off among speed,power and area,pipelined SAR ADC is the newest research direction of ADC with low power consumption,medium-high speed and medium-high precision.The basic principle and design method of the two-stage pipelined SAR ADC is studied,and its linearity,power consumption,area and speed are analyzed.Then,the amplifier-based two-stage pipelined SAR ADC is studied.To reduce the power and design difficulty,the zero-crossing-based two-stage pipelined SAR ADC is proposed,where the amplifier is replaced by the zero-crossing detector and current source.Based on SMIC 180 nm CMOS technology,a 10-bit 50MS/s amplifier-based twostage pipelined SAR ADC and a 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC are designed.The former consumes 5m W with the ENOB of 9.02-bit resulting in the Fo M of 192 f J/conv.-step.The latter consumes 5m W with the ENOB of 10.76-bit resulting in the Fo M of 57.7 f J/conv.-step.According to the test results,the performance of the zero-crossing-based two-stage pipelined SAR ADC is significantly better than that of the amplifier-based one.With the same power consumption,two-bit resolution is improved in the zero-crossing-based two-stage pipelined SAR ADC,which meets the demand of low power consumption in the current application market.Reconfigurable SAR ADC is one kind of the new hybrid SAR ADC which can be reconstructed to different resolutions and bandwidths according to the system requirements.It is widely used in the multi-frequency and multi-mode systems to improve power consumption and area utilization.In this dissertation,a split capacitor reused and channel time-interleaved technique is proposed,which realizes the synchronous reconstruction of the resolution and bandwidth.In addition,a novel two-step switching method is proposed to reduce the power and area.Finally,a digital background calibration is proposed which can be used to calibrate the channel mismatch for most time-interleaved ADCs.This technique also suppresses the channel mismatch of the proposed reconfigurable method.Based on SMIC 180 nm CMOS technology,a 10-12 bits 80-20 MS/s resolution and bandwidth reconfigurable SAR ADC is design.In the 10-bit 80MS/s mode,the peak DNL and INL is-0.31/+0.47 LSB and-0.71/+0.65 LSB,respectively.With the input frequency of 31.3MHz,the ENOB is 9.13-bit and the power consumption is 2.61 m W resulting in the Fo M of 74.4 f J/conv.-step.In the 11-bit 40MS/s mode,the peak DNL and INL is-0.31/+0.47 LSB and-0.71/+0.65 LSB,respectively.With the input frequency of 15.6 MHz,the ENOB is 9.87-bit,and the power consumption is 2.05 m W resulting in the Fo M of 70.2 f J/conv.-step.In the 12-bit 20MS/s mode,the peak DNL and INL is-0.51/+0.45 LSB and-1.01/+0.98 LSB,respectively.With the input frequency of 7.8 MHz,the ENOB is 10.44-bit,and the power consumption is 1.77 m W resulting in the Fo M of 63.7 f J/conv.-step.