Research Of The Key Technology In14-BIT 200MS/s Pipeline ADC

Pipeline analog-to-digital converters(ADCs)are widely used in instruments and communication devices,whose resolution,speed and power play an important role in the systems.14-bit 200 MS/s pipeline ADCs are suitable for telecommunication base stations and narrowband radar systems and thes kinds of ADCs have relatively high spurious-free-dynamic-range(SFDR)and signal-to-noise-distortion-ratio(SNDR),thereby becoming a research hotspot in academic and industrial areas.With the development of CMOS process,the inherent gain of CMOS transistors decrease,resulting in the degradation of the amplifier's gain.To remove the non-linearity from the finite gain of the amplifier,digital calibrations are usually employed,including foreground and background calibrations.The other factor that limit the ADC accuracy is the matching of capacitors.A digital calibration is also needed to decrease the area and power.This dissertation focuses on some key analog circuits,digital foreground calibration methods and background calibration schemes to achieve high power efficiency.The main work and creative points of the thesis include:(1)do some research on the non-ideal factors of pipeline ADCs and analyze the design targets of the key modules qualitatively and quantificationally.Design a system suitable for the targets and obtain the sampling capacitance and bits in each pipeline stages and verify its rationality through simulations.(2)improve the design of a clock generator of various phases in sample-hold-amplifier-less front end.The circuit is constructed according to the phase relationships.Simulation results show that the phase relations can keep proper when the environment is changing;design amplifiers,comparators and other circuits.(3)employ foreground calibration of capacitor mismatches.Employ a gain selecting scheme by extending the foreground calibration.In the first pipeline stage,the power-hungry gain-boosting amplifier is replaced by a local positive feedback circuit.To obtain the optimum operation point,all different error codes are compared to select the way that the amplifier has the maximum gain.The calibration algorithm is similar to that in capacitor mismatch calibration and is suitable for integration.(4)propose a signal-independent background calibration for insufficient gain of amplifier and capacitor mismatches.By inserting a shuffling between the sub-ADC and the multiplying-digital-to-analog-converter,the dither signal can be randomly injected to a digital window.Finally,the bit weights can converge at almost the same speed.Besides,the signal amplitude has no effect on the calibration work.The algorithm also monitors the swing of the residue voltage and confine it by adjusting the threshold voltage of the comparators,thereby avoiding a large residue swing.MATLAB simulation results show that,the SFDR is improved from 60.7 dB to 98.6 dB and SNDR is improved by from 39.7 dB to 84.7 dB,respectively.(5)Also propose a background calibration for kick-back effect in SHA-less front end by injecting a dither signal in one of the split sampling capacitors.The kick-back coefficient is extracted using correlation algorithm.Three capacitors are also added to inject three independent dither signals to achieve linear and 3rd nonlinear error coefficients.MATLAB simulation results show that it can improve SFDR from 56.4 dB to 90.4 dB and SNDR from 51 dB and to 69.9 dB,respectively.A 14-bit 200 MS/s pipeline ADC that fully integrates pipeline stages,clock buffer,bandgap reference,reference buffer as well as digital foreground calibration module,is fabricated in a 0.18 um CMOS process.The core area is 8 mm2 while consuming about 252 mW(LVDS,reference clock buffer not included)@200 MHz sampling rate and 70 MHz input.The measurement result@200 MS/s shows that SFDR is 82.2 dB,SNDR is 66 dB and ENOB is about 10.7bits,resulting in a Waldon FOM of 757 fJ/conv-step.Therefore,using the system structure and calibration scheme,it can meet most of the design targets.