Research On Programming Model And Architectural Design For Reconfigurable Processor With High Flexibility

The trade-off between flexibility and energy efficiency of contemporary computing chips has created a boom in the field of domain-specific architectures in recent years.The reconfigurable processor combines the high flexibility of the general-purpose processor originated from mutable functionality in time domain,and the high energy-efficiency of the application-specific integrated circuit originated from dataflow execution in space domain,which is a research hotspot of domain-specific architectures.However,the application domains of current reconfigurable processors are focused on regular applications,with poor applicability for irregular applications.There are two reasons for this phenomenon:(1)The existing reconfigurable computing programming method is inefficient to mine the parallelism in irregular applications;(2)The reconfigurable architecture for irregular applications is highly complex,which is difficult to be integrated into mainstream programming model to reduce the difficulty of using the new features of reconfigurable architecture.This dissertation studies reconfigurable processors that support irregular application domains,and proposes programming models and hardware architectures that deal with irregular applications to improve the flexibility of reconfigurable processors.Based on the above two difficulties,this dissertation proposes custom programming models for irregular application domains,and the collaborative design of architecture characteristics and programming models targeting irregular applications.Four technical solutions are proposed as follows.First,the dissertation proposes a parallel programming model for fine-grained parallelism in irregular applications.By providing a new programming method to allow programmers to describe the inter-task dependencies,and provide an aggressive execution mechanism on the reconfigurable processor,this solution outperforms existing OpenCL programming model for reconfigurable processor by at least one order-of-magnitude.Second,the dissertation proposes a transactional programming model for dynamic data structures.By allowing programmers to write dynamic data structures with transactional programming,and using reconfigurable processor resources in space to provide transaction execution mechanisms,this solution increases the throughput of concurrent data structures by 5.18 times compared to fine-grained locking algorithm on reconfigurable processor.Third,the dissertation designs a hybrid-granularity dynamic reconfigurable array and its corresponding programming model.By designing a streamlined processing unit and interconnected network that integrate both coarse-grained and fine-grained datapaths,programmers can use complex control flows.In this way the average utilization of reconfigurable processing units increased from 73.75% to 92.25%.Fourth,the dissertation designs multi-array shared programmable scrachpads,and extends existing programming method for shared data by providing a streaming mode and a privatized mode.By this means,when the number of reconfigurable arrays increases from 1 to 4,performance of application with streaming features and privatized data increases by 4.06 and 4.23 times respectively.Combined with the above solutions,this dissertation implements a reconfigurable processor with high flexibility.The processor is taped out on a 4.83 x 4.93 mm2 silicon in TSMC 65 nm technology under 280-MHz.With an average power consumption of297 mW,this processor achieves 26.38 and 9.52 times better energy-efficiency compared to Atom N550 and Cortex A15 processors for 13 application domains.In short,the technical solutions proposed in this dissertation can extend the application domains of reconfigurable processors to irregular applications,thereby improving the flexibility of reconfigurable processors.