Domain-specific Reconfigurable Computing Structure

With the development of the semiconductor industry and ever increasing complexity of the applications, reconfigurable computing has been a hot spot in the area of microelectronics, electrical engineering and computer science. As a computing mode in both time and space domain, it could customize specific computing parts by utilizing reconfigurable logic units, as well as achieve different computing tasks by reusing resources. A more flexible and efficient reconfigurable computing architecture could be achieved by analyzing and optimizing algorithms from specific domains. This paper begins at domain specific reconfigurable computing and performs some useful explorations and attempts, major work includes:Firstly, some of the domain specific algorithms have been investigated, which include digital signal processing, image video multimedia, communication and cryptography. Basic operations are extracted by analyzing these algorithms. Among them, constant multiplication is frequently used. It occupies 20 percent of the multiplication operations. The adder-shifter-mux based constant multipliers show area advantages over traditional multipliers when there are multiple outputs and the configuration number is less than six.Secondly, the current constant multiplication implementations will pay a great area penalty when solving multiple standards and multiple outputs problems. An optimized reconfigurable multiple constant multiplication (RMCM) algorithm is then presented. It applies two fusing strategies, that is, local optimization and global optimization. The topology similarity of the multiple constant multipliers is found to be fused, and the adders are shared in both space and time domain. A unified constant multiplier generation software tool is also presented to produce all forms of the hardware of the constant multipliers.Thirdly, a reconfigurable multi-transform VLSI architecture supporting video codec design is implemented by using the RMCM algorithm. This architecture is suitable for the transform processing with real-time 1080P HD video codec design of four mainstream video coding standards. The static reconfiguration is for different standards while the dynamic reconfiguration is for forward and inverse transform. It is synthesized using 130-nm technology with the area of 23060 gates and working frequency of 100MHz. Finally, a novel coarse-grained reconfigurable computing unit is described. The architecture includes configurable adders/subtractors, configurable shifters, multiplexers and complementers. It is capable of performing many kinds of addition and multiplication based operations. This application-driven computing unit requires no instructions, the computation on which are configuration-based and could exploit data parallelism to a large degree. Furthermore, it could be integrated as a processing element for multicore architecture. It is synthesized using 130-nm technology with the area of 2964 gates and working frequency of 55MHz.