Architectural Research And Implementation On Reconfigurable Computing System

The new generation applications such as wireless communication, digital media, mobile computing in today's fast-growing embedded market segment, put strict requirements on speed, power, integration, cost and flexibility of electronic devices. Robustness, weight, volume, etc are more important in military and aerospace area. However neither the software execution mode based on general purpose processor (GPP) or hardware execution mode based on ASIC meets all of these requirements well. Firstly, GPP instructions are executed serially. The lack of enough functional units and instructions limits its performance. Secondly, it's difficult and costly to make an ASIC chip in despite of its performance. ASIC does well in a very huge volume only. As the life-cycle of consumer electronics become shorter and shorter, the advantage of ASIC is disappearing. The new emerging high-capacity FPGA is surpassing ASIC. The reconfigurable computing (RC) mode based-on FPGA fills the gap between GPP and ASIC. Because of its high-performance and flexibility, RC finds good trade-off amongst all the requirement factors, and is spreading widely.Reconfigurable computing is a new computing diagram on temporal-spatial domain. The RC system often consists of lots of programmable logic and routing resources. It performs well because algorithms are implemented on hardware and executed in a fully-parallel manner. Meanwhile, the system will adjust its hardware dynamically according to the algorithm's run-time character, so that the hardware will be highly optimized for the data width and computing mode. Good flexibility and adaptability could be achieved.Along with the semiconductor's history, RC was originally implemented on the user-made programmable device, later the general device such as FPGA. Many architectural specifications of RC are purposed from the diverse hardware fabrics.