Analysis Of Key Characteristics Of Through-Silicon-Via(TSV)-Based Three-Dimensional Integrited Circuits (3D ICs)

With the continuous development of semiconductor technology node, theconventional planar integrated circuits (ICs) scaling have reached limits that aredifficult to surpass. The chip scaling and functionality increase result in interconnectdelay increase, limiting IC performance and increasing power consumption.Three-dimensional (3D) ICs has emerged as an effective approach to overcome theselimitations.3D ICs could bring multiple design disciplines (Digital, Analog, RF) on asingle chip by stacking semiconductor layers on top of each other, and sustaincontinuous increase in functionality, performance and integration density indefinitely.Through-silicon-via (TSV) is the core technology that provides a verticalinterconnection with greatly reduced wire length among the stacked dies. In this paper,the characterizations of TSV-based3D ICs are studied, the main results obtained asfollows:1、The parasitic parameters of different TSV profiles have been studied, withparticular emphasis on the capacitance model of tapered TSV. Firstly, by solvingPoisson’s equation, an analytical model for the parasitic capacitance of tapered TSVwith MOS effect is proposed. Secondly, a comparison between the analytical model andAnsoft Q3D parameter extraction one is given based on copper TSV. The results showthat in the bias voltage of-0.4V,0.5V and1V, for the tapered TSV slop wall angle of75°,80°,85°and90°four cases, the maximum root mean square (RMS) errors ofanalytical model are6.12%,4.37%,3.34%and4.84%, respectively, over a wide rangeof multiple parameters; when MOS effect is ignored, the maximum RMS errors are210.42%,214.81%,214.52%and211.47%, respectively, which prove that the analyticalmodel is accurate and MOS effect is necessary to the analytical model. Finally, thesignal integrity of tapered TSV has also been studied by employing ANSYS’ HFSS. It isshown that, the maximum damping of S11are about19dB by considering MOS effect,so the transmission performance of tapered TSV is improved.2、The thermo-machanical performances of TSVs have been studied. Firstly,accurate analytical models for the strain and stress in silicon induced by annular andcoaxial TSVs are proposed. Secondly, finite element method (FEM) is used for themodel verification. It is shown that errors for analytical models of annular and coaxialTSVs are respectively less than6.8%and5.6%for various metal and dielectricmaterials. Finally, based on the analytical models of stresses, thermo-mechanicalperformances of annular and coaxial TSVs are studied. It is shown for Cu and SiO2 filled TSVs that,1) pMOS transistors are more sensitive to the stress than nMOS ones.2) W exhibits the best thermo-mechanical performance with KOZ=0; Very closedresults are shown for Al and Cu; TSVs with BCB have the worst thermao-machanicalperformences than other dielectric materials.3) for the coaxial TSV filled with the mostcommon materials, Cu and SiO2, the smaller the sizes of metal portions, especiallysections adjacent to silicon, the better the thermo-machanical performance; the changesof sizes of dielectric portions and TSV heights have silght impact on the thermalstresses.3、A novel TSV structure, the double-annular TSV, is proposed. Various metal anddielectric materials are examined for the thermo-mechanical and electrical performancesof double-annular TSV. Using FEM, it is found that the redunctions of KOZ andequivalent area caused by thermal stress of double-annular TSV reach88.9%and22.6%,respectively, compared with that of coaxial TSV for both pMOS and nMOS using Cuand SiO2. The analytical model of stress induced by double-annular TSV is developedwith an average relative error of less than~6.7%for all the materials as compared toFEM results. Besides, by employing ANSYS’ HFSS, double-annular TSV is proved tooffer the same superior signal integrity with coaxial TSV, improving S21by93%at20GHz compare with cylindrical and annular TSVs. The results indicate benefits ofdouble-annular TSV.4、Temperature characteristics of the top layer of3D IC have been studied. By theintroduction of TSV area scale factor r, an analytical thermal model aiming at the toplayer of3D IC taking TSV into account was proposed. This model was analyzed byMatlab software. It is shown that, the temperature of the top layer of3D IC increaseslinearly, as the layer number increases; for the same number layers of3D IC, thetemperature is lower after considering TSVs under the same working conditions; thegreater the scale factor r, the lower the temperature; for more layers and smaller r, thetemperature increases sharply with the decrease of r; and the best range of TSV arearatio factor r is0.5%~1%for an8-layer3D IC, considering both the temperature andarea.5、Temperature characteristics of muticore3D IC have been studied by taking3Dchip-multiprocessors (CMP) for instance. Firstly, an expression of thermal resistancematrix is given. Secondly, transient temperature characteristics of3D CMP are studied.Finally, effect of heat capacity, thermal resistance and power consumption ontemperature is analyzed. It shows that steady temperature of3D CMP is limited effectively by reducing thermal resistance and power consumption; heat capacity, whichinfluences rise time of temperature, does not affect steady temperature.