Design And Implementation Of High Speed Low Power SAR ADC

With the continuous advancement of information communication and Internet of Things technology,more and more electronic devices are used in various fields such as biosensing,smart security,smart city and location navigation.Continuous analog signals in nature need to be quantified by ADC(Analog to Digital Converter),and the digital information can be processed and transmitted in a better way.SAR(Successive-Approximation-Register)ADC is a common ADC architecture.It has the characteristics of simple architecture,low power consumption,and close compatibility with digital circuits.It can continue to follow the development of semiconductor processes.In recent years,high-speed SAR ADCs,which are emerging ADCs,are changing with each passing day and are popular solutions for high-speed ADCs.Due to development in CMOS technology and the proposal of asynchronous clock technology,high-speed SAR ADCs have large power and area advantages over other architectures with equal accuracy.However,most high-speed asynchronous clocks that rely on delays are highly sensitive to PVT(Process Voltage Temperature)fluctuations and are not suitable for harsh working environments.Therefore,it is of great significance to design a high-speed,low-power SAR ADC chip with resistance to PVT fluctuations.This paper designed a high-speed and low-power SAR ADC chip using in satellite navigation or wireless communication.The main work and innovations are as follows:1?Aiming at the phenomenon of input-output differential feedthrough due to the coupling the input voltage.2?The pre-amplifier in the comparator can isolate noise.It is found in the simulation that substrate modulation in the extreme PVT condition.3?Aiming at the high sensitivity to PVT conditions of high-speed asynchronous timing dynamically.4?To solve the problem that the voltage setting on the high capacitor is slow limiting the5?According to the application conditions of the half-swing input,a configurable bypassThe designed SAR ADC chip uses SMIC40nm 1P8M standard CMOS process,and the core area is 0.04 mm~2.The simulation results show that the chip can work in a wide temperature range of-40?to 125?at a sampling rate of 80MS/s.When the differential input is 1Vpp,it can reach SNDR of not less than 63.1 d B at each process corners,spurious-free dynamic range is greater than 75 d B and power consumption is less than 2.5 m W.The chip has been taped out in SMIC40nm process and packaged by Silan.The results show that the chip has the correct function.The test results show that the designed SAR ADC works normally under 1.1V power supply,the conversion rate reaches 40MHz,the effective number of bits is 9.9bits,the dynamic spurious range is 73.7d B,and the power consumption is 1.68m W.There is a certain gap between the measured performance and the simulation results,and the possible causes of this phenomenon are analyzed in this paper.