Resource aware floorplanning of partially reconfigurable designs on heterogeneous FPGA

The floorplanning problem in FPGA has been a topic of research for more than a decade. Although the floorplanning problem has been thoroughly explored for homogeneous FPGAs, very little work has been done for heterogeneous FPGAs. In this thesis, we have designed a floorplanner for Partially Reconfigurable (PR) designs in FPGA that smartly decides one of the three proposed resource allocation schemes to floorplan a particular type of reconfigurable region. We also proposed a White Space Detection algorithm for efficient management of white space inside an FPGA in order to reduce area and wirelength. The floorplanner uses Xilinx Virtex 5 and Artix 7 FPGA architectures and can be easily integrated with existing vendor supplied Place and Route tools. The main objective of the floorplanner is to reduce wirelength, minimize wasted resources and the area. We have compared our proposed floorplanner with other previously published results reported in the literature. We observe substantial improvement in the overall wirelength as well as the execution time.