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Efficient Mechanisms For Supporting Crash Consistency In Persistent Memory Systems

Posted on:2016-09-28Degree:DoctorType:Dissertation
Country:ChinaCandidate:J L RenFull Text:PDF
GTID:1318330536950282Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
Non-volatile memories (NVMs), such as flash, phase-change memory (PCM) and ReRAM, feature both the persistence capability of external storage and the high perfor-mance of internal memory. They promise persistent memory, an emerging tier in the memory and storage stack. Persistent memory has the potential to significantly increase the efficiency of the current system architecture.Persistent memory systems ensure durability of memory data on system failures such as power outages and system crashes. This distinctive feature can save overheads of tradi-tional data persistence mechanisms, but introduces a critical challenge:crash consistency of memory data. In order to guarantee such crash consistency, programs are typically con-strained in accessing memory data by a certain form of software interface. The interface choice and its corresponding crash consistency mechanism largely determine the system performance and the ease of programming.This dissertation presents my research on efficient mechanisms for supporting crash consistency in persistent memory systems, under three main forms of interfaces:file sys-tem, transactional memory, and the software-transparent interface. Main contributions of this dissertation include the following.·For file systems, we introduce atomic transactions to the page cache of an operating system to ensure that memory data is flushed to persistent storage in a consistent manner. This technique is applied to smartphones whose DRAM and flash can be deemed as a persistent memory system. In order to optimize the energy efficiency and app responsiveness of smartphones, we design app/user-adaptive policies and algorithms to quantitatively trade off data staleness for energy efficiency/app re-sponsiveness.·For transactional memories, we propose a new buffering and group commit de-sign, small buffer array, according to the characteristics of (potentially NVRAM-enhanced) NVM Express-attached SSD. It largely reduces the waiting latency in group commit, while saturating the bandwidth of the flash device. Moreover, we employ snapshot isolation to hide write latency from the critical path of read-only transactions, which brings significant performance improvement to real-time ana-lytical workloads.·With software-transparent interfaces, programs can safely access memory data us-ing regular load/store instructions. Programmers do not need bother partitioning transient and persistent data or writing transactional code, but enjoy unmodified legacy code and better portability than using a particular transaction library. We establish the importance of this software-transparent approach and, to enable the approach, propose an efficient consistent dual-scheme checkpointing mechanism which synchronously checkpoints memory data at different granularities.·Dual-scheme checkpointing brings a new challenge to the crash consistency guar-antee:the isolation and maintenance of multiple versions of data are complicated by the overlap of program execution and checkpointing. We propose to use a state machine to model the consistency protocol, and formally prove the correctness of the protocol.
Keywords/Search Tags:memory, persistence, non-volatile, transactional memory, checkpointing
PDF Full Text Request
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