Developing representative workloads for future hardware transactional memory research using a cycle-accurate, multidimensional hardware transactional memory model

Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Transactional memory provides a means to bridge the discrepancies between programmer productivity and the difficulty in exploiting thread-level parallelism gains offered by emerging chip multiprocessors. Because the hardware has outpaced the software, there are very few modern multithreaded benchmarks available and even fewer for transactional memory researchers. To make this problem worse, the architecture community has no means of characterizing the similarity of the benchmarks that do exist, which poses serious questions concerning the comprehensiveness of current evaluations. This hurdle must be overcome for transactional memory research to mature and gain widespread acceptance. Currently, for performance evaluations, most researchers rely on manually converted lock-based multithreaded workloads or the small group of programs written explicitly for transactional memory. A new parameterized methodology that can automatically generate a program based on the desired high-level program characteristics benefits the transactional memory community.;In this work, all of the above issues are addressed. First, a cycle-accurate, multiple-issue multi-core hardware transactional memory model that is capable of simulating each of the three most common dimensions of hardware transactional memory is developed - the first of its kind. That model is then used to perform the first comprehensive study of the interaction that occurs between transactional memory and multi-core architecture. The results of that study are used to develop analytical models that are capable of predicting performance. A set of transaction-oriented workload characteristics is proposed that can accurately capture the behavior of transactional code and, when used in conjunction with principle component analysis and clustering algorithms, expose the similarity that exists in current transactional workloads. Methods to reduce overlap (the number of required simulations) and maximize the comprehensiveness of an evaluation based upon the architectural areas of interest to the transactional developer are described in detail. All of these tools and experience gained are used to develop TransPlant, a framework that is capable of generating synthesized transactional benchmarks based on an array of different inputs. It is shown that TransPlant can mimic the behavior of current transactional memory workloads. Further, TransPlant is shown to be capable of generating benchmarks with features that lie outside the boundary occupied by traditional benchmarks. Finally, TransPlant is used to perform a case study on the behavior of future transactional memory workloads. (Full text of this dissertation may be available via the University of Florida Libraries web site. Please check http://www.uflib.ufl.edu/etd.html)...