Design Of 12-bit Time-interleaved Pipeline ADC And Research On Mismatch Between Channels

Anolog-to-Digital Converters(ADCs) with high-performance are more and more widely used in national defense, communication and high-end home appliance and other fields. It is a common key technology in electronic information industry. As long as the development of the electronic information fields, the operating speed of all kinds of communication devices is becoming faster and faster, which results in active demand of high-speed ADCs.For traditional structure ADCs, on the premise of high precision, speed of ADCs is almost reaching the limitation of process. Therefore, parallelization is an effective way to break the constraint of conversion rate and without sacrifice of precision at the same time. There exists inherent disadvantage in parallel ADCs. Offset mismatch, gain mismatch and sample-time error among channels generate reducing accuracy of the ADCs, which needs calibration method to eliminate error.In this paper, a 12 bit 50MHz pipeline ADC of one channel based on CMOS Smic0.18 um process is designed firstly, which reaches 70.3581 d B of SNDR, 77.9108 d B of SFDR and 11.5137 of ENOB with a 561.523 k Hz input of sine wave. Then, the reasons resulting in error between two-channel Pipeline ADC had been analyzed in detail. After mathematical derivation to quantizing the effect of offset mismatch, gain mismatch and sample-time error to system accuracy, error models were built in Matlab to simulate and verify the influence in ADC performance. In terms of correcting errors, a calibration method based on LMS-FIR and CIC interpolation filter was adopted, which is included in a two-channel time-interleaved 12 bit, 100 MHz Pipeline ADC. According to the simulation results, the SFDR of the system increased 45.03 d B after correction, which reached to 75.98 d B.