The Key UHF RFID Reader Modules And Single-chip Transceiver Design

With the wide application of radio frequency identification (UHF RFID)technology, single-chip reader has become a key and hot spots in the study of UHFRFID technology. According to the UHF RFID-related protocol specifications andrequirements, taking key modules and single-chip transceiver as the study target, thefollowing work has been complete:The basic theory of UHF RFID system is analyzed and makes a study on thetheory of energy transfer between the reader and tag. The advantage anddisadvantage of different structures of the RF transceiver is summarized. The readertransceiver modules and overall performance is determined by analyzing theISO/IEC18000-6C air interface protocol.A missing low noise amplifier with high linearity reader transceiver structure isproposed. The transmitter path is designed according to the emission spectrum maskrequirements in the protocol. For the transmitter design using a third-orderChebyshev low-pass active filter as a baseband signal pulse shaping filter for itoccupies a small chip area. In the design of power amplifier, use a two-level linearstructure AB class amplifier and the output stage uses linear upgrade technologicalat the same time which guarantee the linearity of power amplifier.A3.5/4prescaler is used in the design of the ΔΣ Fractional-N frequencysynthesizer. A quadrature voltage controlled oscillator is applied in the frequencysynthesizer, for it can output four channels of high-precision-matching of orthogonalsignals without design a layout matching multiphase filter. A3.5/4prescaler canmake theΔΣ modulator quantitative step down to half compare to integerfrequency divider, reducing the frequency synthesizer band phase noise.A quadrature downconversion mixer is designed in the receiver path; currentinjection technology is used in the downconversion mixer design to reduce theflicker noise effectively and so reduce the noise figure. Two different automatic gaincontrol circuit loops were designed: In the first automatic gain control circuit atraditional peak detector is used to detect the output amplitude as a control signal forthe feedback loop. In the design of another automatic gain control circuit, comparingthe output signal with a reference signal to generate a square wave signal which dutycycle changes with the amplitude of the output signal. A charge-pump controlled bythe above square wave to charge and discharge a capacitor for generating the control signal of the automatic gain control ciecuit loop.In the layout design of the transceiver tow effective isolation technology ispresented and a single-chip reader transceiver is realized by CMOS process. Thereceiver and transmitter path has been tested individually and the performance ofsingle-chip reader transceiver is summarized at last.