The Design And Implementation Of Single Event Effects Testing System For The Large Scale Digital Logic Devices

Radiation induced Single Event Effects(SEEs) are increasing threats to the electronic systems in the space applications, even those in the ground applications. SEEs can cause upsets of the stored information, malfunctions(even corruptions) of the systems. Therefore, the SEE susceptibility of the devices intended to be applied in the harsh environments must be tested to verify which are acceptable. The harden methods are also should be adopted in the design of the systems to tolerate the SEEs. Heavy-ion experiment is one of the most important approaches of the hardness assurance tests and verifications of the mitigation methods. While the Heavy Ion Research Facility in Lanzhou(HIRFL) is a very good experiment platform.To evaluate the sensibility of the electronic devices to the SEEs, and to verify the harden methods, a SEE testing system which features flexibility, robustness and compatibility is designed and constructed based on the HIRFL. In which, a lot of approaches of design and strategies of stability are introduced. The testing system is architected well enough to meet the requirements of functions and performances, and to keep experimenters away from the damages of the radiations. The testing system is constructed in a motherboard-daughterboard structure. The motherboard is designed to accomplish the required functions, while the daughterboards are designed to load DUTs. The daughterboards can be connected to the motherboard by several ways. It just needs change daughterboards when the DUT is changed. It is of benefit to the universality, flexibility and cost of the system by reusing the motherboard. The testing system provides 120 single-end and 40 pairs of differential channels, which support several level standards in 1.5V, 1.8V, 2.5V, 3.3V, and with a high bandwidth which is no less than 200 Msps, to the DUTs. Consequently, many types of digital devices with various scales and interfaces are compatible. The testing system has two core units. One is the control and monitoring units. It monitors the operating statuses of the testing system to protect the system form the breakdown caused by the inefficient heat sink and the irradiation by the stray ions from the beams of the accelerators. The other one is the testing unit which is cored on a field-programmable gate array(FPGA). With the unit, various test plans and schemes can be implemented by configuring the FPGA with the designed logic. Benefiting from the advantages mentioned above, not only the current test plans can be satisfied, but also the future test plans can be achieved.With the testing system, kinds of SRAMs and several FPGAs are test in the HIRFL. The experiments prove that the testing system is designed well enough for the requirements of SEE testing, and reveal some phenomenons. In the experiments of the SRAMs, the testing system can detect the single event upsets(SEUs), including the single bit upsets(SBUs) and the multiple bits upsets(MBUs), and the single event latchups(SELs) occurred in the SRAMs. And the details of the SEUs and SELs, such as the occurring time, the positions, the upset data, can be collected. This is useful for the researches of the SEEs. On this basis, the analyses show that the error correction coding(ECC) can affect the cross section of the SEUs, but also loses efficacy in some scenario. The analyses also show that the temperature can affect the cross section. After the experiments of the SRAMs, several FPGAs are tested. In the experiments of the FPGAs, the testing system can detect the SEUs and SELs occurred in the FPGAs. Thus the SEE susceptibility of the FPGAs is assessed. Besides, the effectiveness of the harden method using triple modular redundancy(TMR) is also estimated. The preliminary results indicate that TMR is helpful for the reliability of the system.