Study Of Single Event Effects On SOI FinFET Device And Combinational Circuit

The influence of Short Channel Effect and charge sharing in semiconductor device became more and more serious with the development of manufacture technology, the limits of planar technology were more and more obvious. Due to the advantages of lower power dissipation and higher speed, nano-sized Fin FET process emerges to be a good solution. Because of its 3-D structure, Fin FET process was more suitable for higher density integrated circuits. SOI was proposed many years ago. Compared to traditional bulk silicon devices and circuits, SOI devices and circuits have the advantages of higher speed, lower power,higher integration level and no latch-up effect. The SOI Fin FET combines the best sides of SOI technology and Fin FET technology. Due to better isolation and stronger gate control capability, SOI FINEFT was proved highly potential for radiation harden device. However, if the radiation strengthening was only implemented in device level, the cost will be extremely high. The radiation strengthening method should be considered in device level, transistor level and system level simultaneously, which will be inexpensive and effective.In this paper, single event effect has been studied. The drain leakage current of the device was observed to compare with others, which may lead to soft errors in the circuit. A single-fin SOI Fin FET and a double-fin SOI Fin FET 3-D model of 28 nm process were established in the Sentaurus TCAD software, and the heavy ion model in the software was used to simulate the energetic particle. The drain leakage currents of different devices under same radiation environment were compared to find out the better structure of radiation strengthens. Moreover, the drain leakage currents of same device under different radiation environments were compared to find out key factors in single event effect. Drain leakage currents variation with time were extracted from four different factors, which were drain bias, LET values, injection positions and temperatures. The worst case that affects the device of energetic particle injection was obtained. The result shows that drain leakage currents increase with bigger LET, and with stronger drain bias. The most sensitive position of single-fin SOI Fin FET was near the drain well, for double-fin Fin FET, the position was near the drain well and at the middle of double fins. Temperature affect the current slightly, drain current under higher temperature was weaker slightly. The result also shows that the double-fin structure was less sensitive to SEE than single-fin structure.Based on the results of device simulation, mixed level simulation of single event effect on CMOS inverter was performed using Sentaurus TCAD software. Simulation of single event effect on inverter was carried out, what's more, some radiation-hard circuits were discussed and studied. One of the strengthening circuit is composed of standard pull-up network, standard pull-down network, strengthening pull-up network, strengthening pull-down network, high level error correction network and low level error correction network, which have strong immunity against single event effect. Moreover, that technology can apply to all standard CMOS combinational circuit. However, the area of radiation-hard circuit is two times or more than the standard one. Fortunately, the reinforcement network is not necessary to be the replica of standard pull-up and pull-down network, which can cover all situations. Usually, strengthening the output is not required for all input values but only for those who have no logical masking in the propagation path up to the next memory element or output, therefore, the area overhead is substantially reduced without the loss of reliability. At the last of this paper, the methods of logical masking were discussed.