Research On RETs And Hotspot Detection For Nanometer-scale Circuits

Following Moore’s Law, IC industry has evolved into nanometer scale. Lithography is the key step in IC manufacturing, however, due to the slow development of illuminations system,193nm lithography is still the main choice of IC industry. When the IC developed into sub-90nm technology node, using193nm lithography to manufacture design layout will lead to heavy optical proximity effect (OPE). To compensate for OPE, many resolution enhancement technologies (RETs) have been proposed to improve the imaging quality of layout patterns in IC industry, such as optical proximity correction (OPC) technology, off-axis illumination (OAI) technology, immersion lithography (IL) technology and etc. With continuous evolution of IC technology node, more improvements and innovations are needed for existing RETs. On the other hand, hotspot patterns still exist even after kinds of RETs have been applied to the design layout. Hotspot detection is the process to find these hotspot patterns in design stage and guide the fixing process of design layout, which is one of the most popular domains in the researches of design for manufacturability (DFM) technology of IC. The main contents and innovations of this paper focus on the following two aspects, RETs and hotspot detection for nanometer-scale circuits:Support vector machine (SVM) based layout retargeting algorithm for inverse lithography technology (ILT). ILT, also known as pixel-based OPC, is able to get better optimized layout for its more flexibility in modifying the original layout design. To ease the slow convergence and time-consuming of ILT, a SVM based layout retargeting algorithm is proposed in this thesis. By studying of existing optimized result to train SVM models and using these models to optimize each pixel on the layout, retargeted layout generated by this method is very close to the final optimized layout. By using this retargeted layout as the initial input layout of ILT, we can reduce the iterations needed in the optimization process and decrease the time consumed. Differentiated layout hierarchy managing method for OPC. For parallel operation of OPC and reduction of time consumed in correction of the entire layout, hierarchy managing is needed to cut the original layout into sub layouts and correct them independently. To take advantage of the hierarchy information in the original layout design, a differentiated layout hierarchy managing method is proposed in this thesis. After partitioning of the similar areas and dissimilar areas by similar areas identification method, flat hierarchy managing is applied to the dissimilar areas, and environment identification based on cells used to find same cells with same environments is applied to similar areas, after which OPC of these cells executes once and results of it are reused in the hierarchy managing method for similar areas.A multi-objective layout decomposition algorithm for self-aligned double patterning (SADP). Double patterning technology is one of the main choices for sub-32nm IC manufacturing; SADP has drawn many attentions of researchers due to its intrinsic ability in avoiding overlay impact. Layout decomposition is the key step for SADP to handle2-D patterns, and a multi-objective layout decomposition algorithm for SADP is proposed in this thesis. By adding more constraints in original satisfactory (SAT) problem based algorithm, optimized decomposition results are obtained with our algorithm, including improvements as follows:density distribution of core mask layout is improved by graph theoretic based initial decomposition; rate of edges impacted by overlay is reduced by constraining the way of imaging for selected edges, and overlapping of boundaries on trim mask and boundaries of sidewall in the same direction are forbidden, so as to avoid patterns not belonging to original layout design generated under overlay impact; complexity of resulting layouts is reduced by constrain the minimal length of edges.Improved machine learning based hotspot detection algorithm. Due to its high detection speed and capability of detecting unknown hotspot, machine learning based hotspot detection method has become one of the top domains in hotspot detection researches. To further improve the detection speed and detection accuracy, existing methods are enhanced with sparse matrix feature encoding method and modified hierarchically detection method proposed in this thesis. The sparse matrix feature encoding method reduces the non-zero elements of encoded vector at the same time of remaining different vectors of different layout patterns, which is able to accelerate the computing of kernel function and improve the hotspot detection speed. A third classifier is added to the modified hierarchically hotspot detection method, so as to reduce the impact of conventional method on the rate of hotspots not be detected when to reduce the rate of falsely detected hotspots, and enhance the hotspot detection accuracy.