A Window-based Double Patterning Layout Decomposition Method

With the feature size of integrated circuits shrinking continuously,the 193 nm wavelength lithography has reached its resolution limit.In the short term,Extreme Ultraviolet Lithography(EUVL)is difficult to put into mass production.In this case,Double Patterning Technology(DPT)has become the most effective way to solve the problem of lithography.However,under the space constraints of DPT,such decomposition is not always feasible,especially in metal layers with complex features.In this case,designers have to insert stitches to split the pattern into two parts to resolve the conflict.But too many stitches will lead to degradation of lithography quality,resulting in circuit failure.In order to reduce the number of stitches introduced during the double patterning layout decomposition process,this paper presents a window-based double patterning layout decomposition method.The specific steps are : 1)According to the actual size of the routed layout,this paper virtualizes it into a square.2)Fracture the layout polygons into rectangles to get prepared for odd cycle construction using pattern matching.3)According to the size of the expanded layout,divide it into several windows for iteration.4)Extracts the patterns across the windows,then decompose them using odd cycle and do not modify them firstly in following steps.5)Construct odd cycle within each iteration window and complete decomposition through window iteration.The experimental results of the M2 layers of three benchmark circuits c5315,c7552,s38417 under 45 nm process indicates that the window-based double patterning layout decomposition method can reduce stitches 11.34%,14.38%,8.1% respectively compared to ordinary method.After lithography simulation,the window-based double patterning layout decomposition method can reduce hotspots by 17.54%,15.58%,13.15% respectively compared to ordinary method.