Research Of Low Power IR-UWB Communication System-on-Chip Based On CMOS Technology

Ultra-Wideband (UWB) technology can provide high data rate, low power low cost, short range wireless links, and it has great potential in short distance wireless communication field. Because of its low transmission power, it can coexist with the current wireless communication systems, which can ease the increasingly tense band resource requirements. The design and implementation of low cost low power UWB chip is the key of UWB technlogy toward to the market applications,863program and National Science and Technology Major Project have supported this research for several times. The difficulty lies in the RF front-end in a UWB communication system. The modulation scheme and system structure determine the complexity and power consumption of the system. OOK modulation is the simplest of all modulation schemes, and the most significant advantage is that it can use the non-coherent receiver with simple structure, so it can achieve low power consumption. The System-on-Chip (SoC) is the way to achieve the lowest power consumption. SoC chip includes RF front-end of transceiver and baseband, and no one has realized the SoC chip over UWB band in our country. This thesis focuses on the implementation of Impulse Radio Ulta-WideBand (IR-UWB) On-Off keying (OOK) modulation communication system based on CMOS process and the design of high speed ADC in the receiver of coherent system.The transmitter is based on the switch-controlled oscillator, circuit works only when data comes, the rest of time is turned off, so as to realize OOK modulation and reduce power consumption.3～5GHz transmitter is based on0.18μm CMOS process, it is part of the OOK communication system SoC chip, and the energy efficiency is15.3pJ/pulse when the pulse repetition frequency (PRF) is100Mbps. The SoC communication demonstration system is capable of high-definition video transmission, and the distance is2m. A low power output driver for6-9GHz band is designed in the thesis, and the6-9GHz transmitter is based on0.13μm CMOS process. The energy efficiency of this transmnsiter is6.4pJ/pulse when PRF is100Mbps and6pJ/pulse when PRF is500Mbps, the power consumption is further reduced..The receiver is a non-coherent receiver based on energy detector, including low noise amplifier (LNA), detector and limiting amplifier, the structure is simple and it is easy to achieve low power consumption. This thesis presents a LNA with single-ended input differential output. Simulation results indicate that in the range of 6-9GHz bandwidth, the gain of LNA is29dB and the noise figure is about2.5dB. Meanwhile MOS transistors operating in sub-threshold region are employed to implement a low power detector, the detector only consumes140uA current, and the power consumption is168uW. The limiting amplifier adopts active inductor and current bleeding technique to expand the bandwidth and increase the gain. The receiver is based on0.13μm CMOS process, and the total power consumption is about7.2mW, the highest data rate is up to200Mbps with-the energy efficiency of36pJ/pulse.In addition, the thesis has done some research on coherent system, it can achieve higher data rate and longer transmission distance, but it need a high-speed ADC to sample the output signal of down-mixer, and it is very difficult to implement a high speed high precision ADC and the power consumption is very large. Based on the characteristic that pulse signals have a high compressed ratio in time domain and a high instantaneous SNR, a2bit4GS/s ADC and a1bit2GS/s ADC are designed in this thesis, all the analog part uses differential low-swing current-mode-logic (CML) to achieve high speed and low power consumption. To solve the problems for the interface between the high-speed ADC and the digital baseband, an output convert module is designed, which converts the high speed serial output of the ADC into500Mbps parallel data. Finally the output signals are converted into LVDS standard level by LVDS driver and provided to the off-chip baseband FPGA. The ADC is tested in a wireless communication system, and the bit error rate is less than10-6.