Key Technologies For Strained Si/Ge MOSFETs With Source/Drain Stressors

As MOSFETs keeping scaling down, the conventional bulk Si material does notmeet the performance requirements of the scaled MOSFETs. To boost the performanceof the devices, strain engineering has been widely studied since microelectronicstechnology entered nano regime. Among all the strain technologies, source/drain (S/D)induced channel stress is most attractive because it is fully compatible with theconventional CMOS technology and it can induce uniaxial stress in device channel.Although the strained Si p-MOSFET with SiGe stressors has been adopted in massfabrication in year2003, its n-MOSFET counterpart is still under researching. Themain reason hindering the application of strained n-MOSFET is attributed to the highseries resistance in Si:C S/D stressors. Moreover, there are few reports for strained GeMOSFET since Ge is quite a new material for MOSFET fabrication.To address the problems presented above, the main focus of the thesis is strainedSi/Ge channel MOSFET with S/D stressors. In Si MOSFET, the S/D stressor is siliconcarbon (Si:C), while in Ge MOSFET, the S/D stressor is germanium tin (GeSn).Several key issues in the strained Si/Ge MOSFET are extensively studied in the thesis,which include:1) carbon profile engineering in the Si:C S/D stressors using ionimplantation,2) contact resistance reduction for Si:C S/D MOSFET utilizing aluminum(Al) ion implantation and profile engineering,3) formation of GeSn alloy using ionimplantation followed by rapid thermal anneal or excimer laser anneal, and4) theapplication of GeSn alloy in Ge MOSFET S/D. The details of the study are given asfollows.In the first part of the thesis, a retrograde carbon profile was demonstrated toreduce the resistance in Si:C S/D stressors formed by carbon ion implantation and SPE.The retrograde carbon profile features a30-nm-thick buried Si:C layer that is spatiallydecoupled from a10-nm-thick surface layer with high phosphorus concentration. Thecarbon peak concentration in the buried Si:C layer is8×1020cm^-3, which is much higherthan the surface carbon concentration featuring3×1020cm^-3. After800C and40sanneal, the substitutional carbon concentration (Csub) and sheet resistance (RS) of the new sample is1.2%and380/square, respectively. The experiment results indicatethat retrograde carbon profile can achieves more than30%reduction of RSwhilereserving high Csubin Si:C S/D stressors. As an additional advantage, nickelmonosilicide (NiSi) formed on Si:C S/D with a retrograde carbon profile has a Rswhich¹0%lower than that formed on Si:C with uniform C profile.In the second part of the thesis, we demonstrated a novel technique to reduce theNiSi contact resistance (Rcon) in strained n-MOSFETs with Si:C S/D stressors, where apre-silicide Al implant was performed and the Al profile is engineered by carbon. Aldiffusion during silicidation is retarded by the presence of C and a high Al concentrationis retained within the NiSi film. The electron barrier height of NiSi reduced to0.44eVafter Al incorporation, which is0.25eV lower than the control sample. The Si:C S/DMOSFET with the new contact shows a S/D series resistivity of684μm and achieves50%reduction in S/D resistance. In the MOSFET with gate length of100nm, thesaturate drive current (IDsat) and peak transconductance (Gm) are enhanced by30%and17%, respectively. According to the statistical experimental results, the IDsatexhibits a12%improvement when off-current is0.5μA/μm. Negligible impact on device shortchannel effects is observed for the new technique. The subthreshold swing and draininduced barrier height lowering (DIBL) are99mV/dec and120mV/V in the devicewith100nm gate length, which are identical to the control sample. Since Al alsolower the hole barrier height for p-MOSFET when locating at the NiSi/Si interface, theAl profile engineering shows a promising way of single-metal-silicide solution forselective Rconoptimization in future CMOS technology.In the third part of the thesis, the growth technique of GeSn was studied as a newapproach to form S/D stressors in strained Ge MOSFET. Sn was incorporated in Gesubstrate by ion implantation and GeSn alloy was formed by SPE for the as-implantedsample. Various Sn implant doses were carried out during the sample preparation,which were2×1015cm-2,4×1015cm-2and8×1015cm-2, respectively. In addition, twodifferent anneal techniques were employed to perform SPE, which were rapid thermalanneal (RTA) and excimer laser anneal (ELA). The experimental results show thatRTA cannot recrystallize the amorphous GeSn layer induced by ion implantation, but itcan activate the Sn atoms in single crystal Ge and form GeSn alloy. Sn activation rateachieves100%when RTA temperature is400C. The substitutional Sn concentration is fixed to1×1021cm^-3and shows no relationship to the initial Sn dose. In contrast,ELA can full recrystallize the amorphous layer perfectly. The GeSn alloy exhibits asmooth surface and free from dislocations. However, the surface segregation of Snduring ELA will significantly reduce the Sn concentration in GeSn alloy. When a ELAwith energy fluence of400mJ/cm2and5pluses is used, the substitutional Sn content is1.7%for the sample with initial Sn dose of8×1015cm-2, which is0.7%less than theRTA sample with the same Sn dose.In the last part of the thesis, GeSn alloy was applied to strained Ge MOSFET S/Dregion and the related properties were studied. The experimental results show that anamorphous region will form when Sn concentration exceeds1×1019cm^-3. Surfacedamage will also occur during Sn implantation, which is caused by the ion sputteringeffect. The depth of the surface crater is30nm when implant energy is35keV. Theamorphous region can be recrystallized by a500C-120s RTA, but the surface craterscannot be removed. There are many defects around the craters, while quite a fewend-of-range (EOR) defeats at the "amorphous region/single crystal" interface. Thetwo kinds of defects will induce sharp increase in leakage current when they are locatednear the depletion region of p-n junction. To achieve a low leakage current, thethickness of GeSn layer should be smaller than the depth of S/D junction and thus theSn implant energy should be lower than35keV. GeSn alloy with a thickness of20nmcan be formed with Sn implant energy of25keV. The substitutional Sn content in theGeSn alloy is2.6%, the sheet resistance is25/â–¡, and the leakage current is smallerthan0.1mA/μm2. The properties of the as-formed GeSn alloy meet the requirementsof strained Ge MOSFET.The new techniques presented in the thesis can reduce the Si:C S/D seriesresistance effectively, and thus improve the drive capability of the strained MOSFETs.The GeSn growth technique also explores a new way to form the GeSn alloy and can beused as references for the Sn implantation and GeSn recrystallization. The new growthtechnique is fully compatible with the conventional CMOS technology and addsminimal cost in the process. However, the GeSn alloy quality is not good enough andneeds to be improved in the following work.