Research On Threshold Voltage Model In Strained Si MOS Devices

By introducing stress into the channel of MOSFET device, strained-silicon technology improves the carrier's mobility, thus enhances the performances of the device. In addition, based on the process of bulk-Si CMOS, strained-silicon technology needs no complex process, is widely applied as a cheap and efficient technology to continue the development of Moore's Law.This thesis revises the material parameters and energy band models of strained-silicon and strained-SiGe devices, establishes two-dimensional Poisson's equations of electric potential distribution in strained-SGOI PMOS device. By using boundary conditions to solve these equations, an accurate threshold voltage model is obtained. Then the correctness of this model is proved by simulation and analysis using Matlab software.In order to solve the problems of strained-device, such as: serious short-channel effects, increase of sub-threshold slope and so on, this thesis presents a novel structure called dual-gate strained-silicon SOI MOSFET, and designs a process which is based on existing CMOS manufacturing process. By solving the two-dimensional Poisson's equations of this device, a threshold voltage model is established. After that, the threshold voltage of this novel structure is simulated using Matlab. The results prove that this dual-gate strained-silicon device can control short-channel effects well and has a minimum gate length of 25nm. With the established threshold voltage model, the effects of changes in key device parameters (such as gate oxide thickness, strained-silicon thickness, composition of Ge, etc.) on device performance are also simulated. According to these simulation results, a set of optimal device parameters are proposed.