The Study On The Design And Key Process Of4H-SiC Power UMOSFETs

Silicon Carbide (SiC), the wide band gap semiconductor material, has outstanding properties such as wide bandgap, high critical breakdown field, higher thermal conductivity, and high electron saturation drift velocity, therefore it is particularly suitable for making the devices operated in high temperature, high voltage and high radiation environment.4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs), with the advantage of high breakdown voltage, low on-resistance, fast switching speed, high-temperature operation and strong radiation resistance, has shown the excellent prospects in the applications of national defense and civilian. The research on4H-SiC material and device fabrication has been the focus in the field of semiconductors and microelectronics technologies. This dissertation mainly discusses the new structural simulation, key fabrication process and characterization. The main contributions of this dissertation are shown as follows:1. The operational mechanism of the4H-SiC UMOSFET and the4H-SiC material models have been investigated. Suitable4H-SiC material models used in numerical simulations such as band-gap, mobility, incomplete ionization have been established. A new analytical model for the current-voltage characteristics of4H-SiC UMOSFET is developed using solving the electrical potential of different drift regions. Then the analytic models of threshold voltage, on resistance and breakdown voltage are presented based on structural parameters of device.2. A new4H-SiC power UMOSFET structure named high-k gate field plate4H-SiC UMOSFET (high-k GFP4H-SiC UMOSFET) is proposed, in which the gate is extended to the drift region and SiO2gate dielectric is replaced by the high-k material. During on state, the majority carrier accumulation layer is formed at the side of the gate field plate, resulting in lower on resistance. During the blocking state, the high-k GFP4H-SiC UMOSFET introduces a new peak electric field in the drift region and changes the body electric field distribution, relieving the electric field crowding effect and enhancing the breakdown voltage. In addition, the interface peak electric field is significantly reduced due to using the high-k gate, and the reliability of device is greatly improved. It indicates from simulations that breakdown voltage is increased by1.5times and on resistance is reduced by30%compared with the conventional4H-SiC UMOSFET.3. The thermal oxide process and the kinetics of wet and dry thermal oxidation of N-type4H-SiC epitaxial layers have been investigated. The influence of the temperature, time, oxidizer and doping concentration on the oxidation rates has been discussed in detail. A modified Deal-Grove model for the4H-SiC thermal oxidation has been also developed. The linear oxidation rate constant B/A and the parabolic oxidation rate constant B are extracted by fitting the measured data to the modified Deal-Grove model, which shows that the oxidation rate are significantly affected by the doping concentration.4. The MIS capacitor characteristics of SiO2/4H-SiC and Al2O3/4H-SiC have been investigated. SiO2/4H-SiC MIS electrical characteristics has been studied with different oxidation processes, such as dry oxyen, wet oxygen and dry+wet oxygen. Interface state, border-trap and oxide charge densities are extracted from the IV and CV characteristics and used to evaluate the interface quality and reliability of the SiO2/4H-SiC MIS structure. It is found that wet oxidation process effectively improves the interface state, the fixed oxide charge and border-trap, howerer, to further improve the compactness、 breakdown characteristic and reduce the leakage current of the SiO2layer, proper dry re-oxidation annealing should be carried out for the wet oxidation samples. Atomic layer deposited (ALD) high-k gate dielectric Al2O3/dry-oxygen oxidized ultrathin SiO2films grown on the8°off-axis4H-SiC (0001) epitaxial wafers are also investigated. The4H-SiC MIS capacitors with different gate dielectric stacks (Al2O3/SiO2, Al2O3and SiO2) are fabricated and compared. Ⅰ-Ⅴ measurements show that the Al2O3/SiO2stack has a higher breakdown field to be comparable to Al2O3, and relatively low gate leakage current to be comparable to SiO2. Ⅰ-Ⅴ and C-Vmeasurements at various temperatures (300-500K) have been performed for the Al2O3/SiO2/4H-SiC MIS, which shows that the maximum accumulation capacitance value is reduced as the test temperature increases, and the gate leakage level is in increase as the temperature increasing. It is deduced that the main leakage mechanism for the Al2O3/SiO2/4H-SiC MIS is the internal thermal electrons emission and trap-assisted tunneling effect at high field and high temperature with analyzing the relationship between the barrier height and temperature.5. The4H-SiC UMOSFET design and key processes have been studied. The device design and the fabrication flows are presented firstly. Then, key processes to fabricate the device have been implemented, which mainly include the ion implantation, activation annealing, ICP etching and P-tpye ohmic contact. The effect of ICP process condition on surface quality and etching rate has been investigated. Results show that a maximum etching rate450nm/min is obtained, and better surface and wall quality can be obtained under the condition of SF6/O2=24/6sccm, bias source power100W and sourece power500W. Multiple-energy aluminium (Al+) implantations into4H-SiC and activation anneal with a graphite encapsulation layer have been performed. Measurements show that the implanted Al+box doping profile is formed and high ion activation ratio of78%has been achieved by40min annealing at1600℃. The step bunching effect associated with the high temperature post implantation activation annealing (PIA) process is dramatically suppressed by the graphite layer. And a flat and smooth surface with a small RMS value of around1.16nm is achieved for the implanted4H-SiC after the PIA process. Two different doping concentration P-type4H-SiC epilayer samples have been used to fabricate ohmic contacts with Ti(50nm)/Al(100nm) and Ti(20nm)/Al(100nm), respectively. The influence of the doping concentration and Al component propotion on the specific contact resistance has been studied, and the lowest specific contact resistance of2.1×10-4Ωcm2has been achieved by linear transmission line method.6. Design and fabrication of the4H-SiC power UMOSFET. Based on the theoretical achievements antecedent,4H-SiC power UMOSFET is designed and fabricated firstly successfully in our country. The device is normally off showing a threshold voltage of6.1V and the leakage current JLK is7.2×10-7A·cm-2@VDS:=12V. The specific on resistance is determined to6.25Ω·cm2at Vgs=15V.