Study On Topology Architecture And Communication Paradigm For Network-on-Chip

As the microelectronics technology expanding, the traditionally idea of System-on-Chip(SoC) to integrate the whole system on a single chip which with only one CPU is in the bus architecture, unable to meet the need of multi-IP architecture development. So several research groups proposed a whole new idea of integrated circuit architecture, Network-on-Chip(NoC). The core idea of NoC is to transplant the knowledge of network technology of computer into the design of chips to systematically solve the problems of bus architecture. In NoC system, topological structures and communication paradigm are important factors in system performance. After in-depth analysis and research in key problems of NoC, we proposed some new solutions to solve the NoC problems. The solutions had been validated by modeling-simulation, software and hardware verification.The main research results of this thesis are shown as follows:1. Research on the topological structures of NoC. Two suitable network-on-chip topologies, that is, Generalized Petersen graph(GP(2m,1)) and the Mesh Connected-Cycles (MCC) interconnect network structures are proposed. We made detailed analysis of the character of the two topologies, designed two deterministic routing algorithms of the new topologies, and make a contrast between the GP(2m,1) and the MCC topologies and the typical mesh topology. The results show that MCC and GP(2m,1) have better performance, especially in local traffics and low loads, and lower cost.2. Research on NoC switching mechanism. A new Buffered Express Wormhole Switching(BEWS) technology of high performance and low cost is proposed. Also a contrast is made between BEWS and typical Virtual Channel Wormhole Switching(VCWS) technology by simulation analysis,which demonstrate BEWS achieves lower latency than VCWS.3. After making a summary of structure and design of the NoC routers, a new router structure based on BEWS for network-on-chip is designed. And detailed design, functional simulation, and performance evaluation are done to the new router structure. The results shows BEWS router has lower lantency.4. Analyzed the NoC system-level modeling simulation, summed up system-level performance evaluating process, and then analyzed and designed system-level-simulation network model and traffic model, finally set up a system-level simulation platform. The platform explores the NoC design space in an expandable way.5. An NoC system, 64 nodes, is designed and verification with FPGA. And synthesis and layout are carried out by SMIC 0. 13μm standard CMOS process and it s hardware scale and power dissipation is 515.5 k logic gate and 308. 5 mW @ 300 MHz for the router, traffic generator and traffic reciever.6. The NoC development and verification platform is set up according to a new design method. The platform united with system-level simulation platform comes to an integrated NoC Development & verification environment with system analysis, functional simulation, hardware verification and performance evaluation functions.7. According to the development trend of NoC, three kinds of topology that suitable for three-dimensional NoC are proposed. They are Hypercube-Connected Double-Loop topology, Torus Connected Petersen Graph topology, Rectangular Twisted Torus Meshes topology. And detailed analysis is made to the three topologies show that the proposed networks is a better interconnection network in the properties of topology and the performance of communication.