Analyzing And Hardening Single-event Transients In Phase-locked Loops

With the rapid development of aerospace, aeronautical and nuclear power applications, electrical systems are facing threatens of radiation effects when exposed in the radiation environment. Analyses and hardening of high-performance analog and mixed-signal circuits have been the key point to enhance reliability because of their complexity and sensibility to radiation effects. Phase-locked loops (PLLs), which are widely used in clock generation and synchronization, can be the representative to study radiation effects in high-performance analog and mixed-signal circuit.As one of the typical radiation effects, single-event transients (SETs) can exert serious effects on the PLL including phase and frequency shift, oscillation temporarily stop, resulting in disastrous consequence to the entire system as data loss in communication links and function interruption in microprocessors. PLLs are sensitive to SETs, in feature of long response time, wide influence range and high complexity in analysis and hardening. And SETs tend to affect the PLL system more seriously with smaller feature size, lower supply voltage and higher operating frequency. Thus, the PLL has become the critical component to be hardened to cope with the challenges brought by SETs.This thesis investigates SET effects of high performance PLLs in deep sub-micron (DSM) CMOS process. It is revealed that analysis methodology of SETs and hardening technique are critical aspects of the research on radiation hardened PLLs. This thesis firstly puts forward SET analysis models of PLLs, then develops a circuit-level SET analysis tool to get a quantitative understanding of the SET phenomenon, and finally the critical components of PLL, such as charge pumps (CPs) and voltage-controlled oscillators (VCOs), are studied and hardened in radiation-hardened-by-design (RHBD) methodology. Main contributions and innovations of this thesis are as below:1. Systematic and circuit-level models of PLLs are established to facilitate SET analysis. For one thing, based on a typical PLL model, a systematic model for characterizing SET effects in CPs is proposed, which chooses the control voltage VC of the VCO as the object to reveal the effects induced by SET current in CPs. This model is conducive to analyze SET response rapidly and meanwhile easy to use with clear relationship and simplicity in simulation and measurement. For the other thing, to improve the generalization of this study, a standard PLL structure is specified with selected components and loop parameters, which is further implemented in 0.18μm CMOS process to hammer a solid basis for SET analyses in circuit level.2. A quantitative analysis tool named SETA (single-event transient analysis) is developed with a complete SET analysis framework to support large scale simulations for SETs in PLLs. Standing on the industrial golden simulation methods and tools for SETs, SETA utilizes the current source to bring SET into circuit simulations and extracts data based on the evaluation system. SETA provides services in various aspects, including behavior modeling, circuit exploring, multi-dimensional stimuli generation, simulation script automatic generation, large scale data process and simulation acceleration. Experiments prove that SETA provides a comprehensive profile of SETs, with advantages of preciseness, flexibility, and effectiveness.3. This thesis studies SET effects in CPs and proposes hardening scheme in RHBD methodology, to reduce the SET sensibility of CPs. Firstly, based on the systematic SET model of PLL, the relationship between SET response and related parameters is studied in time domain and frequency domain respectively. It is found that CP's SET sensitivity can be decreased with optimum loop parameters. Secondly, a set of complementary current limiter (CCL) is proposed to limit SET current in CPs. When SETs affect the CPs, CCL can reduce the disturbance quickly by negative feedback mechanism while influencing little on the PLL loop in the absence of SETs. Moreover, CCL is easy to design and implement. Simulation results of 1 GHz PLL indicate that CCL can reduce SET sensibility of CPs obviously with peak VC disturbance and recovery time reduced to 6.9% and 23.5% as to unhardened, respectively. In addition, CCL can also be used in other applications which need to limit current disturbance.4. The SET effects in VCOs are studied and corresponding RHBD technique is proposed to improve SET resistance. Firstly, how factors, such as injection energy, hit location, hit time, and control voltage/frequency, affect the SET response in the symmetrical load VCO is specified by large scale simulations. It is proved that going through the factors with large scale simulations is effective to guide SET analyses. Secondly, a radiation hardened VCO is designed with low cost and great improvement in SET sensitivity. Furthermore, tradeoff between frequency characteristics and SET resistance is proposed by means of adjusting ring oscillator structures. Compared with previous work, the VCO proposed in this thesis achieves to good SET resistance with lower cost in area, power dissipation, and frequency properties. Experiments manifest that the SET sensitivity of the bias circuit and ring oscillator have been reduced to 14.1% and 7.9% compared to unhardened, respectively.5. To evaluate the effectiveness of the proposed RHBD technique, a SET hardened PLL chip is implemented and fabricated in 0.18μm CMOS process. Experimental measurement results indicate that the PLL works well in the frequency range between 400 MHz and 1360 MHz. Evaluations by SETA reveals that the SET sensitivity of the PLL has been drastically decreased, where peak VC disturbance, erroneous pulses and maximum phase displacement are improved by over 60%, and recovery time is reduced by 25.7%. All the results above prove that the RHBD techniques in this thesis can effectively enhance the overall radiation resistance of PLLs.It can be concluded that the SET analysis tool provides precise evaluations for SET effects with high efficiency, and can be widely applied in SET sensitivity study of PLLs. The proposed RHBD technique decreases SET sensitivity effectively with little impact on the performance of PLL circuits. Though the experiments and concludes are based on PLLs, the methodology and RHBD technique can be extended to a wide range of analog circuits.