Mobility Modeling And Fabrication Of Si/Ge MOSFET With High-k Gate Dielectrics

Silicon dioxide (SiO2) has been scaled aggressively for the past decades for low-power, high-performance CMOS field-effect transistor applications. The SiO2 with physical thickness of 1.2 nm has already been implemented in the 90-nm logic technology node. However, continual gate oxide scaling requires high-k gate dielectric since the gate oxide leakage in SiO2 is increasing with reducing physical thickness and SiO2 will eventually run out of atoms for further scaling. Presently, the high-k gate dielectrics concentrate on Hf-based and Zr-based oxide and oxynitride. As application of the high-k materials as gate dielectric, some problems occur: one is called"Fermi-level pining", which can be solved by replacing poly-Si gate-electrode with metal one, another is degradation of inversion carrier mobility, which is believed to be from remote soft optical phonon scattering. This scattering mechanism is inherent in high-k materials. It is reported that remote soft optical phonon sactering can be partly screened by utilizing metal gate electrode, but it can not be eliminated completely. To improve mobilities of MOSFETs with high-k gate dielectrics, a promising method is to use high-mobility semiconductors, eg. strain Si, SiGe and Ge, to replace Si as channel material. However, high-k dielectrics growed directely on Ge exhibit a poor high-k dielectric/Ge interface properties. So, a stable passivation layer (or interlayer) on surface of Ge with a high k value is pursued to improve interface quality and reduce equivalent oxide thickness. Aiming at the above problems, theoretical and experimental work involving the mobility models of strain SiGe MOSFET and Ge MOSFET with stacked high-k gate and fabrication of MOS devices with high-k gate dielectric are performed to find relevant solutions in this thesis. The content of the thesis is arranged as follows: 1) mobility models on strain SiGe MOSFET and on Ge MOSFET with high-k/interlayer gate stacked; 2) investigation on preparation and electrical properties of Ge MOS capacitors with HfTa-based gate electric and AlON or TaON interlayer; 3) investigation on preparation and electrical properties of Ge MOSFET with HfO2 gate electric and TaON or HfON interlayer.For mobility model on strain SiGe, a semi-experienced low-field hole mobility model of strained Si1-xGex/Si pMOSFET is proposed by considering effect of strain on energy-band structure of SiGe alloy, and coulomb-scattering of interface-trapped charges on inversion carriers is also included in it. Using this model, changes of hole mobility with strain (Ge content) is simulated at and influences of some factors on mobility are discussed. For MOSFET with stacked high-k dielectric, a physical model on mobility degradation by remote interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer (SiO2) thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer as well as moderate permittivities (k~15-25) of high-k dielectrics is highly desired to improve carrier mobility while keeping low equivalent oxide thickness. Simulated results agree reasonably with experimental data.The fabricating process and electric charactristic of Ge MOS capacitors with HfTa-based gate dielectrics and AlON and TaON interlayers are invetigated. At first, the influces of annealing ambient and temperature on electrical characteristics of Ge MOS capacitor with HfTaO gate dielectric is investigated. Thus proper annealing condition, such as annealing temperature (500 oC) and ambient (wet N2), is decided. Then, the electrical properties and reliabilities of HfTa-based oxide and oxynitride with AlON and TaON, or without interlayers on Ge substrate are investigated. The experimental results show that the MOS capacitors with these interlayers exhibit low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness, and high dielectric constant. These should be attributed to a blocking role of ultrathin AlON and TaON interlayer against inter-diffusions of Ge, Hf and Ta, and penetration of O into the Ge substrate, and thus effectively suppresses formation of unstable low-k GeOx and gives a superior interface between high-k and germanium substrate. As comparing stacked gate dielectric of HfTaO(N)/TaON to HfTaO(N)/AlON, the former exbits higher k value and lower capacitance equivalent thickness due to the higher k value of TaON than AlON. In conclusion, Ge MOS device with AlON and TaON as passivation layers is promising method for application of improvement device's performances.Finally, the fabricating process and electric charactristics of Ge pMOSFET with HfO2 gate dielectrics and TaON and HfON interlayers are studied. Experimental results show that the MOS devices with these interlayers exhibit much lower gate leakage current than those with only HfO2 as gate dielectric, good interface properties, good transistor characteristics, and about 1.4-1.9 fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that an ultra-thin interlayer layer of TaON and HfON inserting between germanium substrate and HfO2 dielectric can effectively suppress growth of unstable GeOx, inhibiting inter-diffusion of Hf, Ta and Ge, thus reducing interface states and increasing hole mobility by reducing Coulomb scattering, especially for sample with HfON interlayer, which exhibits more ideal output characteristics and higher mobility than other samples.