Eelectron-mobility Model And Interfacial Properties Of (In)GaAs MOS Devices With Stacked High-k Gate Dielectric

As the characteristic length of MOSFETs is scaled to beyond10-nm technology node, silicon-based CMOS technology is tending to its theoretical limit. In this case, some high-mobility channel materials (e.g. Ge and III-V compound semiconductors) are most likely to replace a strained-silicon channel. Among them,(In)GaAs compound semiconductor is an ideal channel material for preparing n-MOSFETs with ultra-high speed and low power consumption due to its high electron mobility. However, as compared with the SiO2/Si system, the (In)GaAs surface is lack of a stable high-quality native oxide. In order to obtain excellent properties of high-k/(In)GaAs interface, various surface passivation techniques prior to the deposition of high-k gate dielectric have to be performed, including surface chemical processing (e.g. sulfur passivation), plasma treatment or deposition of a thin interfacial passivation layer (IPL) and so on. Use of stacked high-k gate dielectric will introduce remote Coulomb scattering and remote interface roughness scattering, enhancing degradation of channel carrier mobility. Aiming at the above problems in this thesis, various scattering mechanisms on mobility degradation are theoretically analyzed, and thus an electron mobility model for InGaAs n-MOSFET with stacked high-k gate dielectric is established. Experimentally, a series of meaningful investigations are carried out to improve interfacial and electrical properties of (In)GaAs MOS devices with stacked high-k gate dielectric.Theoretically, based on the analyses on various scattering mechanisms for mobility degradation of two-dimensional electron gas in channel, a physics-based electron-mobility model is established for InGaAs n-MOSFET with stacked high-k gate dielectric. Influences of the remote Coulomb and interface-roughness scatterings on electron mobility are focused on, and effects of physical and structural parameters of the devices, including thickness and permittivity of the interlayer and high-k dielectric, fixed charge in the high-k dielectric, correlation length and interface roughness, on electron transportation properties in channel are analyzed in detail. The simulated results indicate that in order to get both small equivalent oxide thickness (EOT) and high electron mobility, the interlayer and high-k gate dielectric should have the optimum thickness matching (e.g.～1nm for interlayer and～3 nm for high-k gate dielectric) and reasonably high dielectric constant (e.g.-14for interlayer and～30for high-k gate dielectric), and at the same time, the deposition technologies of the gate dielectric should be optimized to minimize both the fixed charge in the high-k dielectric and the roughness of the high-k/interlayer interface.Experimentally, HfTiON/interlayer/GaAs MOS capacitors are firstly fabricated by using TaON, AlON and GGO as IPL on sulfur-passivated GaAs substrate respectively. By investigating the influences of two post-deposition annealing (PDA) temperatures and atmospheres (NH3, N2) on interfacial and electrical characteristics of the devices, the appropriate PDA temperature (600℃) and atmosphere (NH3) are determined. Measured results of electrical properties for the three samples with different IPL showed that their interface qualities are improved, with low interface-state density, low gate leakage current and high device reliability, in which the HfTiON/TaON/GaAs MOS with TaON as IPL exhibits the lowest interface-state density (～1.0×102cm-2eV-1), the smallest gate leakage current density (7.3×10-5Acm-2at Vg=Vfb+1V), the smallest capacitance equivalent thickness (CET=1.65nm) and the largest equivalent dielectric constant (26.2).On the basis of the above experimental investigations, further using plasma-nitrided GGO as IPL and HfTiON as gate dielectric, HfTiON/GGON/InGaAs MOS capacitor is fabricated. On the other hand, InGaAs MOS capacitor with composite gate dielectric consisting of multilayer TiON/TaON is fabricated by RF magnetron sputtering method. The experimental results show that the both surface-passivation methods can effectively suppress the formation of the interfacial In/Ga/As oxides and remove excess As atoms at the InGaAs surface, greatly reducing the relevant defects and unpinning Femi level at the high-k/InGaAs interface, and thus obtaining good interface properties, low gate leakage current, small CET, high equivalent k value and device reliability. As compared with the NH3-plasma treatment of GGO, the composite gate dielectric of the multilayer TiON/TaON has relatively simple processing and better stability without absorption of moisture. Therefore, the composite gate dielectric of multilayer TiON/TaON exhibits a great potential in preparing high-performance InGaAs-based MOSFETs.