Interlayer Material,Structure And Passivation Processing Of Ge MOS Devices With High-k Gate Dielectric

As the characteristic length of MOSFETs is scaled to beyond 10-nm technology node,silicon-based CMOS technology is tending to its theoretical limit.In this case,some high-mobility channel materials(e.g.Ge and III-V compound semiconductors)are most likely to replace a strained-silicon channel.Among them,Ge compound semiconductor is an ideal channel material for preparing p-MOSFETs with ultra-high speed and low power consumption due to its high holes mobility.However,as compared with the SiO2/Si system,the Ge surface is lack of a stable high-quality native oxide.In order to obtain excellent properties of high-k/Ge interface,various surface passivation techniques prior to the deposition of high-k gate dielectric have to be performed,including surface chemical processing,plasma treatment or deposition of a thin interfacial passivation layer(IPL)and so on.Use of IPL will introduce cause the change of threshold voltage,thus influence on device performance.Aiming at the above problems in this thesis,various mechanisms on threshold voltage are theoretically analyzed,and thus a threshold voltage model for Ge p-MOSFET with stacked high-k gate dielectric is established.Experimentally,a series of meaningful investigations are carried out to improve interfacial and electrical properties of Ge MOS devices with stacked high-k gate dielectric.Experimentally,HfTiON/interlayer/Ge MOS capacitors are firstly fabricated by using GGON,TaYON and ZrLaON as IPL on Ge substrate respectively.By investigating the influences of atmospheres(N2)and fluorine incorporation on interfacial and electrical characteristics of the devices,the passivation process are determined.Measured results of electrical properties for the three samples with different IPL showed that their interface qualities are improved,with low interface-state density,low gate leakage current and high device reliability,in which the HfTiON/TaYON/Gc MOS with TaYON as IPL exhibits the lowest interface-state density(?2.5×cm-2cV-1),the smallest gate leakage current density(2.47×10-5 Acm-2 at Vg=Vfb+1 V),the smallest capacitance equivalent thickness(CET=1.14 nm)and the largest equivalent dielectric constant(24.9).On the basis of the above experimental investigations,further using NbON/Si and LaON/Si as dual IPL and HfTiON/HfLaON as gate dielectric,HfLaON/NbON/Si/Ge MOS and HfTiON/LaON/Si/Ge MOS capacitors are fabricated.On the other hand,Ge MOS capacitor with composite gate dielectric consisting of multilayer ZrON/TaON is fabricated by RF magnetron sputtering method.The experimental results show that the both surface-passivation methods can effectively suppress the formation of the interfacial Ge oxides,greatly reducing the relevant defects at the high-k/Ge interface,and thus obtaining good interface properties,low gate leakage current,small CET,high equivalent k value and device reliability.As compared with the stack dielectric of the HfLaON/NbSiON and HfTiON/LaSiON,the composite gate dielectric of the multilayer ZrON/TaON has better stability.Therefore,the composite gate dielectric of multilayer ZrON/TaON exhibits a great potential in preparing high-performance Ge-based MOSFETs.Theoretically,by solving poisson equation,considering the short channel effect(SCE)and leakage barrier lowering effect(DIBL),a Ge channel threshold voltage model of pMOSFET with passivation layer is established.Device structure and physical parameters are analyzed in detail,including the channel length,the passivation layer thickness,gate oxide thickness,interface under different substrate doping concentrations,and different drain-source voltage to the influence of threshold voltage.On this basis,by considering the quantum effect,a voltage model of pMOSFET with passivation layer and high k gate dielectric is also established.Simulation results are in good agreement with the experimental data.By using this model,the device structure and process parameters to the influence of threshold voltage are analyzed,the main parameters reasonable value range of the small size of Ge pMOSFET are obtained,the model is suitable for the device simulation and design.