Research And Design Of High-speed Column-level ADC For CMOS-TDI Image Sensors

In recent years, with the developments of CMOS process technology and imageprocessing technology, CMOS image sensor has developed rapidly. When thesituation has a low light and the object is moving fast, CMOS image sensors have abad property, which is low SNR. The SNR of the line-array image sensor can beimproved through time-delay-integration (TDI) method, using which the sensor canexpose multiple times towards the same object and accumulate the multiple exposureresults together to improve the SNR because the energy of the signal is increasingfaster than that of the noise during the accumulation.when the CMOS image sensorhas more pixels, the ADC needs a higher sample rate and a smaller size.This paper presents a column-parallel single slope analog to digital converter (SSADC) with a two-step time to digital converter (TDC) to overcome the longconversion time problem in conventional single slope ADC for high-speed CMOSimage sensors. The time interval proportional to the input signal is generated by theramp generator and the comparator, which is digitized by a two-step TDC consistingof coarse and fine conversions to achieve a wide dynamic range and high-precisiontime-interval measurements. A high-linearity ramp voltage is generated by anintegrator and is reset periodically by a MOS switch. This ramp voltage is comparedto the input voltage by a comparator and a pulse signal is generated when the rampvoltage exceeds the input voltage. In the circuit, a two-step10-bit TDC consists of a6-bit counter for the coarse conversion and the delay lines that resolves4bits for thefine conversion. The ramp generator and DLL are shared by all columns, and eachcolumn has a comparator, two delay lines and a counter.Through simulation, the10-bit ADC designed in0.18μm CMOS processachieves1μs conversion time,1.6V input range and the SINAD of51.2dB. The totalpower consumption of the proposed ADC is1.76mW including236.38μW powerconsumption per column.