| As the continual scaling of complementary metal-oxide-semiconductor (CMOS), Si MOS device approaches its fundamental limits, and new channel materials, such as strained Si, strained SiGe alloy and Ge substrate and so on, are explored to improve device performance by enhancing carrier mobility in the channel region. Recently, study on SiGe or Ge MOSFETs with high-κgate dielectric have become hot point, which mainly be focused on fabrication processes and electrical properties of high-κgate dielectric. However, post-deposition anneal, surface pretreatment of substrate, and Hf-based oxides doped Ti, were less involved. Also, the studies on modeling of Ge MOS devices, e.g. threshold voltage model and gate leakage model, were rarely reported too. In this thesis, theoritical and experiment work related to above problems is performed to find relevant solutions. Content of the thesis is devided into three parts: 1) threshold voltage model on SiGe pMOSFET, 2) gate leakage model on Ge MOS, 3) preparations and electrical properties of high-κgate dielectric MOS devices with Hf- and HfTi-based oxide and oxynitride as gate dielectric.In this work, analytical models on threshold voltage of deep sub-micron SiGe pMOSFETs with high-κgate-dielectric and Si cap layer or without Si cap layer are respectively proposed by considering short-channel effect (SCE), drain-induced barrier lowing (DIBL) and quantumn effect. The simulated results are in good agreement with experimental data. Based on the model, the main parameters of high-κgate dielectric SiGe pMOSFET can be reasonably determined. For gate-leakage current model, based on the Wentzel-Kramer-Brillouin (WKB) approach, a compact analytical model of Ge MOS device has been developed by taking direct and F-N tunnels into account. Simulated results exhibit a good agreement with experimental data, indicating that the model is suitable for simulating gate leakage current in inversion for deep-submicron Ge MOSFET with stack high-κgate dielectric. However, small error occurs for low gate bias below 0.3 V, probably due to deficiently calculating effects of hole density and trap charges.MOS devices fabricating process and electric charactristic with HfTi oxidation and oxynitride gate dielectric is investigated as followed. (1) HfTiN gate dielectric films are deposited on n-Ge substrates by the method of reacting magnetron sputtering in N2+Ar ambient, followed by PDA which was carried out at 550°C for 300s in a wet N2 ambient instead of O2 to convert HfTiN into HfTiON by utilizing the residual O2 in PDA system, and super performace for Ge MOS capacitor with HfTiON gate dielectric have been achieved with equivalent oxide thickness of 2.4 nm, equivalent oxide charge density of 2.8×1011 cm-2, interface-state density of 5.9×1011 eV-1 cm-2 and gate leakage current of 4.7×10-4 A cm2 at Vg = 1 V. The effects of dry and wet N2 anneal on dielectrice perporities have been investigated too, results indicate that wet N2 anneal for deposited HfTiN film can induce a great reduction of interface-state/dielectric-charge densities and gate leakage current due to the suppressed growth of the GeOx interlayer in the wet ambient. This should be attributed to the hydrolysable property of GeOx in water-vapor. (2) Ultra-thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet N2 anneal. The effects of Ti content on the performances of HfTiO gate dielectricd are analysed by using different sputtering powers of the Ti target. Experimental results indicate that as the Ti content increases, theκvalue can increase up to 40 for the highest Ti content being studied in this paper. However, while the Ti content is too high, the interface properties and gate leakage properties are deteriorated severely. To inspect the influences of PDA on MOS capacitors, PDA was comparatively carried out in wet N2, NH3, NO and N2O ambiences respectively. Results show that excellent dielectric performance is achieved by wet N2 annealing: equivalent oxide thickness of 0.81 nm, relative permittitivy of 35, interface-state density of 6.4×1011 eV-1 cm-2, equivalent oxide charge density of 1.96×1011 cm-2 and gate leakage current of 2.71×10-4 Acm-2 at Vg = 1 V. (3) GeOxNy and GeOxNy /HfTiO stack gate dielectric has been fabricated on Ge substrate with substrate surface pretreatment.Results indicate that surface pretreatment in wet NO ambient is propitious to fabricate sub-2nm high-κGeOxNy/HfTiO gate stack Ge MOSFETs by decreasing density of interface state and equivalent oxide charge, thus reduces gate leakage current and enhances reliability of device.Excellent device performances of GeOxNy/HfTiO Ge MOS capacitor have been achieved with equivalent oxide thickness of 1.88 nm, equivalent oxide charge density of 9.77×1010 cm-2, interface-state density of 2.41×1011 eV-1 cm-2 and gate leakage current of 4.75×10-5 Acm-2 at Vg = 1 V.
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