Model And Technology Of High-k Gate Dielectric MOS Devices

With aggressive reduction of MOS device deminsions into the deep submicrometer regime, the rapid gate leakage current increase results in the device performance degradation. For reducing the gate leakage current, alterative of SiO2 ? high-k gate dielectric is a good choice. The Hf and HfTi oxide and oxynitride have currently become hot point of study due to their higher k value and good thermal stabilization. Theoritically, some models were established about tunneling current of gate for high-k dielectric MOS devices, which, however, are mainly suitable for a gate-oxide voltage |Vox| above 1 V, with many fitting parameters. Experimentally, study on pretreatment technology of Hf-based oxide was less investigated, and study on HfTi-based oxide and oxynitride were mainly focused on properties of HfTiO material, the optimum Ti content in HfTiO dielectric, micro-structure and so on. The study on interface properties between the gate dielectric and Si substrate was less involved. In this thesis, theoritical and experiment work involving the above problems is performed to find relevant solutions. Content of the thesis is devided into three parts: 1) tunneling-current model, 2) preparation and electrical properties of high-k dielectric MOS devices with Hf- and HfTi-based oxide and oxynitride as gate dielectric, and 3) threshold-voltage model and sub-threshold properties of high-k gate dielectric MOSFET.For gate tunneling-current model, two methods are employed: self-consistent solution and analystic methods. Using self-consistent numerical solution, the subband energy, charge density of Si surface and tunneling current of ultra-thin gate dielectric MOS devices is calculated and simulated. The tunneling-current model provides a good fit to experiment data. The dependence of tunneling current with doping concentration in Si substrate and gate dielectric thickness is simulated too. The simulation results indicate that the tunneling current increases with doping concentration decreasing in low gate voltage and the tunneling current only can be change with gate dielectric thickness in high gate voltage. The analytic model is researched in depletion/inversion region and accumulation region respectively. (1) Based on an analytic surface potential model, a tunneling current analytic model with one fitting parameter in depletion/inversion is developed replaced multi-subbands with a single subband. The simulated results are in good agreement with the results from self-consistent solution and experimental data of Si3N4, HfO2 and stack dielectric HfO2/SiO2, with a much shorter computing time than self-consistent solution method. This is a feature work in high-k research area. (2) Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO2 and high-k dielectric material as gate dielectrics respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO2/HfSiON with a U-shape nitrogen profile and a like-Si/SiO2 interface, which is first proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric for MOS memory. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO2 and 1.2-nm HfSiON exhibits the lowest gate leakage.MOS devices fabricating process and electric charactristic with Hf and HfTi oxidation and oxynitride gate dielectric is researched. (1) HfO2 gate dielectric films are deposited on n-Si (100) substrates by the method of reacting magnetron sputtering and different pretreatments and annealing conditions. A O2+CHCl3(TCE) pretreatments is first applied in the fabricating process MOS capacitor with HfO2 gate dielectric. Analysis of leakage current and SILC effects shows that interface properties is improved obviously by O2+CHCl3(TCE) pretreatments, and also the gate leakage current decrease and SILC effects are weakened. (2) MOS capacitor fabricating process and electric characteristic with HfTiON high-k gate dielectric is researched. First, HfTiO dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O2 ambient, followed by an anneal in different gas ambients of N2, NO and NH3 at 600 0C for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. Second, HfTiN film is deposited by reactive co-sputtering and then annealed in O2 or N2O ambients at a temperature of 650 0C for 2 min to form HfTiON films. Capacitance-voltage and gate-leakage characteristics are measured. Results indicate that the N2O-annealed sample exhibits lower interface-state and dielectric-charge densities, and enhanced reliability. The process that the HfTiN is deposited and subsequent anneals with N2O ambient is potential.Threshold voltage and sub-threshold slope of high-k gate dielectric MOS devices is researched. (1) Threshold voltage and sub-threshold slope of MOSFET using high-k gate dielectrics are detailed analyzed and researched by using PISCES-II simulation in the thesis. After comparing with threshold voltage and sub-threshold slope of MOSFET in various k values the simulated result shows MOSFET's electric characteristic is more excellent when the gate dielectrics k<50 and tox/L<0.2 are selected. High-k gate MOSFET threshold voltage mod+el considering quantum mechanical and short channel effect indicates that the impact of quantum mechanical effect on the threshold voltage of short-channel MOSFET is less than the threshold voltage shift of classical model, i.e. short channel threshold voltage model excessly estimates the effect of high-k dielectric while quantum mechanical effect is not considered and the increasing of threshold voltage induced the quantum mechanical effect partly compensates the decrease of threshold voltage caused by short channel effect.