Eot Reduction Method For High-k Metal Gate Structure PMOSFETs At 14nm Nodes

As the scaling of nanodevices continue towards 45nm technology node and below,high-k metal gate structure has replaced the traditional SiO₂ poly-Si structure as one of the research hotspots in the IC industry,to solve the problem of reduced device reliability and excessively increased gate leakage current?Ig?caused by excessively low gate oxide SiO₂ thickness.Among many high-k candidate materials,HfO₂ high-k gate dielectric materials have become the focus of this research.As the continuing miniaturization of the device size,in order to suppress the short channel effect and improve the device's gate control capability,it is necessary to continuously reduce the equivalent oxide thickness?EOT?.To seek the optimal process of reducing high-k metal gate structure PMOSFET EOT and analyze its mechanism,this thesis mainly studies the following three aspects:1.Study on annealing process of Hf-based high k gate dielectric:This content aims to reduce the EOT by improving the film quality of Hf-based high-k gate dielectrics through annealing processes.In this paper,Hf-based high-k gate dielectrics prepared by ALD are annealed under O₂ and N2 annealing conditions,respectively.The experimental results show that O₂ and N2 annealing can reduce the defects in HfO₂,When the O₂ annealing temperature is greater than or equal to 650?,the interface layer obviously thickens,which leads to the increase of EOT,which is mainly due to excess oxygen caused by the interface layer growth.Compared with O₂ annealing,N2 annealing has a larger temperature control process window.2.Study on annealing process of Al-doped Hf-based gate dielectric:In order to solve the problem of excessive gate leakage current of pur HfO₂,a small amount of A1 was doped into pure Hf02,and the quality of the high-k dielectric layer was improved by N2 annealing.Experiments show that A1 doping can change the crystal phase of the HfO₂ gate dielectric,increase the k value of the high-k gate dielectric,thereby reducing the EOT and meeting the 14/16 nm technology node requirements.3.Effect of TiN thickness on EOT:TiN prepared by ALD can not only act as a barrier between the metal gate and the high-k gate dielectric,but also has oxygen absorbing effect The growth mode and physical thickness of TiN have a certain influence on EOT.In this experiment,TiN layers with different thicknesses?1-5nm?were prepared,and the electrical characteristics of MOS capacitors were comprehensively analyzed.Finally,the optimal physical thickness of TiN was 2 nm.