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Research On Application-specific Routing Algorithm In Network On Chip

Posted on:2012-04-13Degree:MasterType:Thesis
Country:ChinaCandidate:H J LinFull Text:PDF
GTID:2248330395455710Subject:Computer software and theory
Abstract/Summary:PDF Full Text Request
As an improvement on System-on-Chip(SoC), Network-on-Chip (NoC) is anintercommunication-based network system, which is implemented on an integratedcircuit. NoC solves the communication bottleneck issue of SoC. However, most SoCsare heterogeneous, the existing NoC design suitable for general system can not meet thequality-of-service oriented, predictable interconnects. Customized NoC for specificapplications, that is application-specific NoCs, eliminate much of the overheadsconnected with general-purpose communication architectures, to maximize theadaptability and performance of communication.Routing technology is an important factor wihich affects NoC area, delay,throughput and power consumption, etc. This paper do some researchs fromapplication-specific routing algorithms as follows.Firstly, in the study of existing application-specific algorithms, we propose a newBandwidth-Aware Routing Technique(BART). Making full use of the knowncommunication mode and flow characteristics, the technique has two phases to solve theuneven load distribution in application-specific NoCs. In the first phase, a genetic-basedmapping technique is used to obtain a near-optimal assignment of IPs to network nodes.In the second phase, a bandwidth-aware rouing algorithm is used to find the minimalroute for each flow in the network. Meanwhile, static virtual channel assignment is alsoused to avid deadlock. The evaluation results show that BART has better performancein throughput and latency than XY routing and Odd-Even Turn Routing. Secondly, forthose NoCs which have partially faulty links, we propose a new Fault-Tolerant RoutingAlgorithm(FTRA) for application-specific NoCs. The algorithm is divided into twostages, in the case of light load, using only error-free routing link, when the load is high,using reconfigurable links to transmit a flit in batches with error-free lines of a link. Inthis way, we can use partially fault links. We have also worked out complete designs ofrouters which can tolerate partial link faults, increasing a traffic condition estimator, asend buffer and a receive buffer. Besides, FTRA combines communication needs of theapplication and changes in the capacity of communication links to avoid congestion andoptimize network performance. The algorithm has characteristics of high throughput,low delay, strong adaptability and deadlock-free.
Keywords/Search Tags:Network on chip, Routing algorithms, Mapping techniques, deadlock, fault-tolerant
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