Single Event Effect Detection And Mitigation Techniques For Spaceborne Signal Processing Platform

Satellite technology plays a growing important role in national economy and revolution in military affairs, which is characteristic of informationization. And with the development of technology, satellite platform or payload relies deeply on very large scale integrated circuit (VLSIC), such as field programmable gate array (FPGA) and digital signal processor (DSP). As the key problem in signal processing platform degign, FPGA and DSP's single event effect (SEE) has been widely concerned ever since its first application in space electronic instrument. With the growth of integrated circuit's scale, high energy particles affect more severely on digital devices. Thus SEE error detection and mitigation techniques should be payed more attention in space electronic instrument design.The research is based on the design of spaceborne TT-C (telemetry, tracking and command) and communication signal processing platform, and aims at improving FPGA and DSP's anti-SEE ability in space environment. Problems such as FPGA and DSP's analytical SEE error model and error characteristic, SEE error detection and mitigation techniques, fault injection-based verification method of SEE hardened design are studied in the thesis. And the main content can be summarized as follow.(1) Based on FPGA and DSP's SEE error characteristic, the thesis proposes a novel analytical SEE error model for FPGA and DSP, and then studies the concomitant characteristic of SEE error, which is a new characteristic in error coupling and propagation. According to the fault injection problem of location-inaccessible errors of FPGA and DSP, a modified SEE fault model is proposed on the basis of SEE error's concomitant characteristic, which can improve the fault coverage and accessible depth of SEE fault injection model. The modified SEE error model gives a new point of view of SEE study for very large scale integration (VLSI) circuit.(2) Based on SEE error's concomitant characteristic, a novel indirect error detection method is proposed from the aspect of FPGA's place and routing strategy,which is named logic probe (LP) and aimed to decrease the losses in resource and performance. Configuration memory's single event upset (SEU) can induce FPGA's multi-block error (SEU-MBE). The thesis analyzes the condition by which SEU-MBE happens and gives two solutions to SEU-MBE, Area Constrain Method (ACM) and Incremental Routing Algorithm (IRA). The proposed approaches show a remarkable increase of SEE immunity for FPGA's routing resource.(3) According to program run flow's disturbance which is induced by the SEU of DSP's PM (program memory) or DM (data memory), the thesis proposes a life-shorten triple modular redundance (LS-TMR) method, a basic block jumping bound monitoring method (JBMM) and a state pulse monitoring method, which can reduce the upset rate of DSP's key variables and the memory consumption of error detection design.(4) On the basis of SEE error detection and mitigation techniques of FPGA and DSP, a pyramid-like monitoring architecture for spaceborne signal processing platform (SSPP) is proposed. The pyramid-like monitoring architecture together with the high efficiency dynamic reconfiguration technique provide a possibility of applying non-radiation hardened FPGA or DSP in space electronic instrument. With the monitoring architecture, FPGA and DSP's anti-SEE reliability increase from 0.63078 and 0.95336 to 0.99045 and 0.99901, when the work period is 24 hours and reconfiguration interval is 0.5 hour.Experimental results show that FPGA's error detection rate is 99.2% and error tolerance rate is 99.6% under the condition of 15% resource increase and 10% speed decrease. Also for DSP, error detection rate is 97.4% and error tolerance rate is 86.0% under the condition of 18% PM increase and 15% run time increase. With the pyramid-like monitoring architecture and the high efficiency dynamic reconfiguration technique, overall error detection and tolerance rate of FPGA and DSP in SSPP can reach to 98.9% and 96.1%.Most of the techniques and conclusions proposed in the thesis have been applied in several satellite spaceborne signal processing platform.