A Research On A Single Event Effect Prediction Of Reinforcement Technology Of VLSI

As is well known,digital integrated circuits are being widely adopt in aerospace field.However,with the continuous development of semiconductor technology and the shrinkage of device size,the impacts of space radiation on integrated circuits are also significantly increased.Especially,highenergy particles can easily cause various problems on chips working in space radiation environment including pulse burr,bit flip,function failure or even complete burnout.These problems put forward higher requirements for the design and test of ASIC.In this thesis,ISCAS89 is taken as a test benchmark circuit.By combining with the main achievements of single event effect research in recent years,a single event effect evaluation scheme suitable for large-scale digital circuits is proposed.Its scheme is as follows:1)Firstly,a transistor-level single event effect model in SPICE(Simulation Program with Integrated Circuits Emphasis)is established for injection and analysis in basic-level circuits.2)Secondly,by using SPICE EDA tool,the ISCAS89 benchmark circuits are implemented with SMIC(Semiconductor Manufacturing International Corporation)180nm process components for simulation analysis.After that,The single event effect model is transformed into the digital logic model described by Verilog HDL(hardware description language).3)By replacing circuits units in original circuits,we can simulate single event effects on largescale digital circuits,and establish the simulation and evaluation process of large-scale digital circuits when single event effect occurs.4)Finally,to achieve the purpose of simulation and analysis of VLSI circuits,based on Python,a script is developed to automatically generate circuit modules and test files for circuits to reduce the workload.Based on the above research,the complete analysis flow from single transistor to VLSI circuit is developed.It can also generate simulation and test files automatically by the Python script,and can be simulated by any EDA tool which supports Verilog HDL simulation.Finally,the simulation and validation for triple-modular redundancy and self-refresh register technology are carried out.Through simulation,it is found that the error rate of the S27 circuit without the reinforcement technology is 0.39% when the single event effect occurs,while the error rate of the circuit is reduced to 0.12% and 0.13% respectively by using the three module redundancy technology and the selfrefresh register technology.The simulation result is reasonable,which verifies the correctness of the single event effect evaluation test scheme.