Research On Demodulator IC Design For OFDM Based DTV Terrestrial Broadcasting

The blooming of digital TV system is quite obvious around the world, which is regarded as the most important reformation in the history of TV broadcasting since last time when the black-white TV is upgraded to colorfulone. It is predicted that this reformation may make big impact on the life style of human beings. The U.S. government has declared the forcible requirement of digital TV standard for all TV venders. Also Chinese government is going to start the high definition television broadcasting for the Beijing Olympics game in 2008, as well as plans to shut down the analog television broadcasting completely and realize the national digit-television service by 2015. Therefore, the demodulator chip design has being the intensive focus of many research groups, which is regarded as one of the core technologies of digital TV systems.This work investigates the development of nowadays digital TV industry and market, and points out that there are several standards in the digital TV terrestrial broadcasting, including the multi-carrier modulation DVB-T and TDS-OFDM systems and the single carrier modulation ADTB-T system. The author concentrates on the OFDM modulation scheme, theoretically and systematically proposes the demodulation algorithm and VLSI architecture of both DVB-T and TDS-OFDM systems based on pilots in frequency domain (DVB-T) and training sequence in time domain (TDS-OFDM) respectively. Noticing that both of the two OFDM based standard may co-exist in the future Chinese market, the author proposes a novel dual mode (TDS-OFDM & DVB-T) demodulator solution with high performance and low cost by effective hardware sharing.As far as the OFDM system synchronization process is concerned, this work proposes several new algorithm and corresponding circuit structure to improve the system synchronization performance: (1) In order to handle the multi-parameters combination in DVB-T system, a novel EWA algorithm is proposed to realize the automatic transmission mode detection with low chip implementation complexity as well increased flexibility and robustness of frame synchronization. (2) This work propose an improved energy center of CIR aided pre-echo mitigation technique to overcome the frame synchronization delay and its ISI and ICI effect caused by conventional maximum likelihood algorithm, which dramatically improves the systemsynchronization performance with rather simple circuit structure. (3) A novel sample frequency synchronization method by utilizing the TPS signaling for TDS-OFDM system is presented, which can lower the huge computation complexity and its corresponding power consumption while keeping the similar circuit structure with the DVB-T system for resource sharing.According to the difference between the frame formats of two systems, the author develops the channel estimation and equalization algorithms for DVB-T and TDS-OFDM system respectively. The channel estimation for DVB-T bases on the interpolation of frequency domain scattered pilots, while that for TDS-OFDM bases on the time domain correlation of training sequence. And the VLSI structures of both methods are described in detail. In addition, the impact of the phase noise on the demodulator performance is discussed and the CPE mitigation technology depending on those pilots information is introduced.In order to increase the efficiency of reuse principle for dual mode demodulator, a multi-points DFT block is invented, which can be configured to calculate 3780, 2K, 4K, or 8K points DFT, with simple configuration setting. Since this work uses the efficient memory sharing scheme with reasonable choice of the DFT pipeline structure and radix of butterfly calculation units, the proposed multi-points DFT block has advantage of flexibility in dual mode demodulator chip design with only a small hardware cost penalty compare to single mode implementation.At last, a complete dual mode demodulator algorithm and architecture is presented based on the algorithm and structure introduced above. The detailed data path and control path definition as well as the block reuse information is demonstrated. After the design of the key blocks of this demodulator, they are verified on a general FPGA verification platform for DTV system. The test results prove that those algorithm and circuit structure proposed in this paper can meet the performance requirements of the specification quite well, and so has promising application potential in DTV area.