Direct Tunneling Processes In Nano-Metal-Oxide Semiconductor Devices

Along with the continuous scaling down of Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET), the thickness of gate oxide layer should be reduced with the channel length in order to control the short channel effect, to decrease the sub-threshold slope and to improve the frequency characteristic. The tunneling rate of the carriers through the gate oxide layer to the gate could increase as the oxide layer become thinner, which results in the appreciable gate leakage currents increasing. Therefore, the direct tunneling currents, instead of the hot-electron injection and Fowler-Nordheim tunneling ones, turn out to be the most important factor to determine the reliability of the devices.On the basis of researching the influence of the quantum effects to the nano-MOS devices, the model of direct tunneling currents has been put forwarded using the sequential tunneling theory and the Bardeen's transfer Hamiltonian formulism. In this model, the tunneling potential profile is detached to several sub-systems. The charge tunneling process can be considered a process the charge moves through these sub-systems sequentially. On the condition of solving the wave-function of the charge in the subsystems, the direct tunneling currents can be carried out.MOSFET memories based on nanocrystals have been considered as most promising application of nanodevices in future very large scale integration. On the basis of analyzing the work mechanism of nanocrystals silicon based memory and the mixing effect of the valence band, the model for the direct tunneling times of electron and hole is developed using the transfer Hamiltonian formalism. The programming and retention times of silicon nanocrystals based memory are calculated numerically, and some influences of the structure and the bias to the performance of device are discussed. It is noted that the new device model should be developed to improve the retention property of silicon nanocrystals based memory.Secondly, we investigate the gate leakage currents numerically for a p+-poly-Si /SiO₂/ n-Si-substrate MOS devices and compare the predicted results with the measured data. The predicted results are excellently consistent with the measured data, which reveals the validity of this model. The leakage currents versus the gate voltages at the different oxide thickness are given. After analyzing these results, we infer that the oxide can be scaled down to 1.5 nm. Therefore, for the MOS devices with the gate silicon dioxide, the thickness of 1.5 nm should be the lower limit of silicon dioxide when scaling down. The further thickness reduction of SiO₂ will results in increasing of standby consumption power and affecting device performance so that the circuits does not work. In order to scale down the MOS devices, the high-κgate dielectrics must be introduced to the devices.The gate leakage currents of the four MOS devices with the Si₃N₄/SiO₂, Al₂O₃/SiO₂, HfO₂/SiO₂ and La₂O₃/SiO₂ gate dielectrics are calculated numerically and the scaling down of the MOS devices with gate stacked dielectrics are discussed. Though Si₃N₄ and Al₂O₃ have the good thermodynamic stability on Si, their relative dielectric constants are too small. Though HfO₂ has the bigger relative dielectric constant, the tunneling barrier for HfO₂ is too low. They could only satisfy the short-term technological requirements. It should be an important subject to develop the gate dielectrics which has very big relative dielectric constants and very high tunneling barriers.